• Journal of Korean Port Research
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• v.15 no.1
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• pp.37-46
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• 2001

Fuzzy logic control(FLC) is composed of three parts : fuzzy rule-bases, membership functions, and scaling factors. Well-defined fuzzy rule-base should contain proper physical intuition on the plant, so are needed lots of experiences of the skillful expert. When membership functions are considered, some parameters on the memberships function such as function shape, support, allocation density should be selected well. The rule of scaling factors is 'scaling'(amplifying or reducing) for both input and output signals of the FLC to fit in the membership function support and to operate the plant intentionally. To get a better performance of the FLC, it is necessary to adjust the parameters of the FLC. In general, the adaptation of the scaling factors is the most effective adjustment scheme, compared with that of the fuzzy rule-base or membership function parameters. This study proposes the adaptation scheme of the scaling factors. When the adaptation is performed on-line, the stability of the adaptive FLC should be guaranteed. The stable FLC system can be designed with stability analysis in the sense of Lyapunov stability. To adapt the scaling factors for the error signals, the concept of the conventional MRAC would be introduced into slightly modified form. A tracking accuracy of the control system would be enhanced by the modified shape and support of the membership function. The simulation is achieved on the pilot plant with the hydraulic steering control of a UCT(Unmanned Container Transporter) of which modeling dynamics have lots of severe uncertainties and modeling errors.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.8
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• pp.2064-2071
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• 1998

A new digital clock level translator has been designed in order to produce a clock source of the internal logic circuits. The translator output has 50% duty ratio from small sinusoidal input such as TCXO which oscillates itself in poratable components. The circuit consists of positive and negative comparators, RS latch, charge pump, and reference vol- tage generator. It detects pulse width of the output waveform and feedbacks the control signal to the input com-parator. It detects pulse width of the output waveform and feedbacks the control signal to the input com-parator reference, producing output waveform with valid 50% duty ratio of the digital signal level. The designed level translator can be used as a sampling clock source of ADC, PLL and the colck source of the clock synthesizer. The circuit wasdesigned in a 0.8.mu.m analog CMOS technology with double metal, double poly, and BSIM3 circuit simulation model. From our experimental results, a stable operating characteristics of 50 +3% duty ratio was obtained from the sinusoidal input wave of 370 mV.

• The KIPS Transactions:PartA
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• v.16A no.1
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• pp.9-16
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• 2009

Because Grid system consists of heterogenous computing resources, which are distributed on a wide scale, it is impossible to efficiently execute applications with scheduling algorithms of a conventional parallel system that, in contrast, aim at homogeneous and controllable resources. To suggest an algorithm that can fully reflect the characteristics of a grid system, our research is focused on examining the type of information used in current scheduling algorithms and consequently, deriving factors that could develop algorithms further. The results from the analysis of these algorithms not only show that static information of resources such as capacity or the number of processors can facilitate the scheduling algorithms but also verified a decrease in efficiency in case of utilizing real time load information of resources due to the intrinsic characteristics of a grid system relatively long computing time, and the need for the means to evade unfeasible resources or ones with slow processing time. In this paper, we propose a new algorithm, which is revised to reflect static information in the logic of WQR(Workqueue Replication) algorithms and show that it provides better performance than the one used in the existing method through simulation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.1A
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• pp.104-112
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• 2005

Some design techniques for high speed and low power pipelined 8-bit ADC are described. To perform high-speed operation with relatively low power consumption, open loop architecture is adopted, while closed loop architecture (with MDAC) is used in conventional pipeline ADC. A distributed track and hold amplifier and a cascading structure are also adopted to increase the sampling rate. To reduce the power consumption and the die area, the number of amplifiers in each stage are optimized and reduced with proposed zero-crossing point generation method. At 500-MHz sampling rate, simulation results show that the power consumption is 210mW including digital logic with 1.8V power supply. And the targeted ADC achieves ENOB of about 8-bit with input frequency up to 200-MHz and input range of 1.2Vpp (Differential). The ADC is designed using a $0.18{\mu}m$ 6-Metal 1-Poly CMOS process and occupies an area of $900{\mu}m{\times}500{\mu}m$

• Journal of Digital Contents Society
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• v.18 no.3
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• pp.607-612
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• 2017

The use of RaspberryPi in building an embedded system may be difficult for users in understanding the circuit and the hardware cost. This paper proposes a solution that can test the systems virtually. The solution consists of three elements; (i) editor, (ii) interpreter and (iii) simulator and provides nine full modules and also allows the users to configure/run/test their own circuits like real environment. The task of abstraction for modules through the actual circuit test was carried out on the basis of the data sheet and the specification provided by the manufacturer. If we can improve the level of quality of our solution, it can be useful in terms of cost reduction and easy learning. To achieve this end, the electrical physics engine, the level of interpreter that can be ported to the actual board, and a generalization of the simulation logic are required.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.7 s.361
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• pp.45-53
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• 2007

In this paper, we propose an efficient hardware architecture for H.264/AVC CAVLC (Context-based Adaptive Variable Length Coding) encoding. Previous CAVLC architectures search all of the coefficients to find statistic characteristics in a block. However, it is unnecessary information that zero coefficients following the last position of a non-zero coefficient when CAVLC encodes residual coefficients. In order to reduce this unnecessary operation, we propose two techniques, which detect the first and last position of non-zero coefficients and arrange non-zero coefficients sequentially. By adopting these two techniques, the required processing time was reduced about 23% compared with previous architecture. It was designed in a hardware description language and total logic gate count is 16.3k using 0.18um standard cell library Simulation results show that our design is capable of real-time processing for $1920{\times}1088\;30fps$ videos at 81MHz.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.5
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• pp.66-76
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• 2000

This paper describes design and implementation of caption-processing ASIC(Application Specific Integrated Circuits) for OSD(On Screen Display) of karaoke system. The OSD of conventional karaoke system was implemented by a general purpose DSP, however this paper suggest a design to save hardware resources. The ASIC receives commands and data of graphic and caption from host processor, and then modifies the data to have various graphic effects. The design has been done by schematic and VHDL coding. The design was verified by logic simulation and FPGA emulation on the real system. The chip was fabricated with 0.8${\mu}{\textrm}{m}$ CMOS SOG, and worked properly at the karaoke system.

• The Journal of the Acoustical Society of Korea
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• v.13 no.2
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• pp.76-85
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• 1994

A speech enhancement algorithm which attenuates nonstationary colored noise is presented In this paper. The algorithm consists of a stationary Kalman filter and the simple speech/nonspeech detector. While the conventional enhancement systems are focused on a stationary and/or white background noise, this study Is focused on the mort realistic nonstationary and nonwhite noise. An AR model-based vector Kalman filter is used as a noise suppression system and a short-time energy threshold logic is used as a speech/nonspeech classifier. For Kalman filtering. noise coefficients are estimated in the nonspeech frame, and speech coefficients are estimated by applying the EM iteration algorithm. Simulation results using the car noise are presented based on the signal-to-noise ratio and informal listening tests. According to the experimental results, background noises in the nonspeech frames are eliminated almost completely, while some distortions are noticed in the speech frames. The distortion becomes severer as the SNR is reduced to 0dB and -5dB. Intelligibility, however, is not degraded significantly.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.7C
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• pp.712-722
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• 2002

We have investigated a novel optical decoder for a fiber-optic code division multiple access(CDMA) communication systems. The conventional optical encoder and decoder have the advantage of simple structure. However the number of users in the system is limited by the auto- and cross-correlation properties generated in decoding process. In previous studies, to improve the system performance, although they used an optical code that minimize the sidelobe and cross-correlation, could not yet find a novel methods for performance improvement in fiber-optic CDMA system. Thus, it is necessary to investigate the novel optical decode in order to improve the performance of system. In this paper, we schematize the AND gate logic element(AGLE) composed with 1$\times$2 or 1$\times$3 coupler and the optical thyristor and propose the novel optical decoder using K(weight) AGLE. The optical thyristor only passes the overlapped signal and clips other signals. Such a novel concept means that the optical thyristor can operate as a hard-limiter. We analyze the fiber-optic CDMA system using the novel optical decoder with simulation and is found that the novel optical decoder using the AGLE and optical thyristor excludes the sidelobe and cross-correlation intensity between any two sequences.

• Transactions of the Korean Society of Mechanical Engineers
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• v.16 no.8
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• pp.1468-1484
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• 1992

In the present paper forward projection is proposed as a new approach to determine the preform shape in rib-web type forging. In the forward projection technique an optimal billet is determined by applying some mathematical relationship between geometrical trials in the initial billet shape and the final products. In forward projection a volume difference between the desired product shape and the final computed shape obtained by the rigid-plastic finite element method is used as a measure of incomplete filling of working material in the die. At first linear inter-/extrapolation is employed to find a proper trial shape for the initial billet and the method is successfully applied to some cases of different aspect ratios of the initial billet. However, when the initial guesses are not sufficiently near the optimal value linear inter-/extrapolation does not render complete die filling. For more general application, a fuzzy system is used in the forward projection technique in order to determine the initial billet shape for rib-web type forging. It has been thus shown that the fuzzy system is more reliable for the preform design in the rib-web type forging process.