• Journal of Institute of Control, Robotics and Systems
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• v.12 no.8
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• pp.834-841
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• 2006

Recently, many enterprises are installing AMSs(Automated Manufacturing Systems) for their competitive advantages. As the level of automation increases, proper design and validation of control logic is a imperative task for the successful operation of AMSs. However, current discrete event simulation methods mainly focus on the performance evaluation. As a result, they lack the modeling capabilities for the detail logic of automated manufacturing system controller. Proposed in this paper is a method of validation of the controller logic for automated material handling system using an object-oriented design and simulation. Using this method, FA engineers can validate the controller logic easily in earlier stage of system design, so they can reduce the time for correcting the logic errors and enhance the productivity of control program development Generated simulation model can also be used as a communication tool among FA engineers who have different experiences and disciplines.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.50 no.1
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• pp.45-50
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• 2001

With increasing complexity of digital logic circuits, fast and accurate verification of functional behaviour becomes most critical bottleneck in meeting time-to-market requirement. This paper presents several techniques for accelerating a cycle-based logic simulation. The acceleration techniques include parallel pattern logic evaluation, circuit size reduction, and the partition of feedback loops in sequential circuits. Among all, the circuit size reduction plays a critical role in maximizing logic simulation speedup by reducing 50% of entire circuit nodes on the average. These techniques are incorporated into a levelized table-driven logic simulation system rather than a compiled-code simulation algorithm. Finally, experimental results are given to demonstrate the effectiveness of the proposed acceleration techniques. Experimental results show more than 27 times performance improvement over single pattern levelized logic simulation.

• Journal of the Korea Society for Simulation
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• v.3 no.1
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• pp.107-114
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• 1994

This paper describes an integrated environment for logic circuit simultion which is an important step of logic circuit design. The system consists of a logic simulator kernel, an expandible element routine library. a functional level element routine generator, several HDL input parsers, and a postprocessor. The system can simulate the same system in several levels of hierarchy. The experimental result shows that the system is very efficient and useful for design of logic circuits.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.5
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• pp.180-187
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• 1996

This paper describes a post-layout simulation method using VHDL and C for verifying the architecture of antifuse-based FPGAs and the dedicated CAD system. An antifuse-based FPGA consists of programming circuitry including decoding logic, logic modules, segmented tracks, antifuses and I/O pads. The VHDL model which includes all these elements is used for logic verification and programming verification of the implemented circuit by reconstructing the logic circuit from the bit-stream generated from layout tool. The implemented circuit comprises of logic modules and routing networks. Since the routing delay of the complex networks is comparable to the delay of the logic module in the FPGA, the accurate post-layout simulation is essential to the FPGA system. In this paper, the C program calculates the delay of the routing netowrks using SPICE, elmore or horowitz delay models and the results feedback to the VHDL simulation. Critical path anc be found from this post-layout simulation results.

• Proceedings of the KIEE Conference
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• 1988.07a
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• pp.579-581
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• 1988

This paper proposes the logic simulation for hierarchical logic network with function descriptor base data structure and algorithm on which a macro cell is considered as a logic elements. Function descriptor base data structure is useful when many logic elements of which type is same exist in a network, for it lessens the computer memory size used during the simulation. And the proposed simulation algorithm may improve the simulation speed.

• Journal of Information Display
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• v.6 no.1
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• pp.17-21
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• 2005

We explored a new way of designing dynamic logic gates with low temperature polysilicon thin film transistors to increase the speed. The proposed architecture of logic gates utilizes the structural advantage of smaller junction capacitance of thin film transistors. This method effectively blocks leakage of current through the thin film transistors. Furthermore, the number of transistors used in logic gates is reduced thereby reducing power consumption and chip area. Through HSPICE .simulation, it is confirmed that the circuit speed is also improved in all logic gates designed.

• 제어로봇시스템학회:학술대회논문집
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• 1996.10b
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• pp.1103-1106
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• 1996

Disturbance Accommodating Attitude control logic for 3-axis stabilized spacecraft is designed and compared with PIID control logic. PID controller provide the zero steady error for constant disturbances. PIID controller detect and cancel disturbances upto the ramp input. PID control logic is designed as the main control logic. We designed the disturbance observer to detect the effect of disturbance using the sinusoidal function. The detected disturbance are compensated by the additional control logic. The comparison simulation is conducted between PIID and PIID with DAC. The simulation results show that PIID with DAC shows the better attitude pointing accuracy.

• Journal of the Korean Solar Energy Society
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• v.32 no.4
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• pp.96-102
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• 2012

The minimum airflow of VAV terminal boxes is a key factor for comfort, indoor air quality(IAQ) and energy cost. If the minimum airflow is not reasonable, it would waste energy and make IAQ problems. There are two types of VAV terminal box control logic. One is the single maximum, another is the dual maximum control logic. Dual maximum control logic is more efficiency way to reduce the energy consumption. It has a minimum airflow set point and a heating maximum set point. It allows the minimum airflow set point to be much lower than single maximum control logic. A building simulation was conducted to evaluate the energy consumption and the IAQ according to the control logic of the V AV terminal box. In the simulation, dual maximum control logic can save the energy up to 6.5% compared to the single maximum control logic.

• Journal of the Korea Society for Simulation
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• v.17 no.3
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• pp.9-18
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• 2008

Unlike conventional researches, we are able to i) compare the fuzzy logic based BBA with non-fuzzy BBA for verifying the effective performance of the proposed fuzzy logic application ii) dynamically respond to the intrusion using BBA whereas the previous IDS was responding statically and iii) expect that this would be a cornerstone for more practical application researches (analyzing vulnerability and examining countermeasures, etc.) of security simulation. Several simulation tests performed on the targer network will illustrate our techniques. And this paper applies fuzzy logic to reduce the false negative that is one of the main problems of IDS. Intrusion detection is complicated decision-making process, which generally involves enormous factors about the monitored system. Fuzzy evaluation component model, which is a decision agent in the distributed IDS, can consider various factors based on fuzzy logic when an intrusion behavior is detected. The performance obtained from the coordination of intrusion detection agent with fuzzy logic is compared against the corresponding non fuzzy type intrusion detection agent. The results of these comparisons allow us to evaluate a relevant improvement on the fuzzy logic based BBA.

• Smart Structures and Systems
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• v.14 no.6
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• pp.1131-1150
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• 2014

One of the issues in extending the range of applicable problems of real-time hybrid simulation is the computation speed of the simulator when large-scale computational models with a large number of DOF are used. In this study, functionality of real-time dynamic simulation of MDOF systems is achieved by creating a logic circuit that performs the step-by-step numerical time integration of the equations of motion of the system. The designed logic circuit can be implemented to an FPGA-based system; FPGA (Field Programmable Gate Array) allows large-scale parallel computing by implementing a number of arithmetic operators within the device. The operator splitting method is used as the numerical time integration scheme. The logic circuit consists of blocks of circuits that perform numerical arithmetic operations that appear in the integration scheme, including addition and multiplication of floating-point numbers, registers to store the intermediate data, and data busses connecting these elements to transmit various information including the floating-point numerical data among them. Case study on several types of linear and nonlinear MDOF system models shows that use of resource sharing in logic synthesis is crucial for effective application of FPGA to real-time dynamic simulation of structural response with time step interval of 1 ms.