Proceedings of the KIEE Conference (대한전기학회:학술대회논문집)
- 1988.07a
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- Pages.579-581
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- 1988
Simulation for hierarchical logic network
계층적 논리 회로의 시뮬레이션
- Lee, H.J. (Hanyang University) ;
- Hur, Y.M. (Hanyang University) ;
- Lee, J.H. (Hanyang University) ;
- Park, H.J. (Hanyang University) ;
- Park, D.G. (Hanyang University) ;
- Lim, I.C. (Hanyang University)
- Published : 1988.07.01
Abstract
This paper proposes the logic simulation for hierarchical logic network with function descriptor base data structure and algorithm on which a macro cell is considered as a logic elements. Function descriptor base data structure is useful when many logic elements of which type is same exist in a network, for it lessens the computer memory size used during the simulation. And the proposed simulation algorithm may improve the simulation speed.
Keywords