• 전자공학회논문지 IE
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• 제44권2호
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• pp.14-20
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• 2007

본 논문에서는 개선된 성능을 갖는 4치 D-플립플롭을 제안하였다. 제안된 4치 D 플립플롭은 뉴런모스를 기반으로 바이어스 인버터, 온도계 코드 출력회로, EX-OR 게이트, 전달 게이트를 이용하여 4치 항등 논리회로(Identity logic circuit)를 구성하고, 이를 2진의 RS 래치 회로와 결합하여 설계하였다. 설계된 회로들은 3.3V 단일 공급 전원에서 $0.35{\mu}m$ 1-poly 6-metal COMS 공정 파라미터 표준조건에서 HSPICE를 사용하여 모의실험 하였다. 모의실험 결과, 본 논문에서 제안된 4치 D 플립플롭은 100MHz 전후까지의 빠른 동작속도로 측정되었으며 PDP(Power dissipation-delay time product)와 FOM(Figure of merit)은 각각 59.3pJ과 33.7로 평가되어졌다.

• 한국전기전자재료학회논문지
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• 제22권10호
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• pp.801-807
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• 2009

In this paper, we propose a novel shoot-through protection circuit and pulse generator for half-bridge driver IC. We designed a robust half-bridge driver IC over a variation of processes and power supplies. The proposed circuit is composed a delay circuit using a beta-multiplier reference. The proposed circuit has a lower variation rate of dead time and pulse-width over variation of processes and supply voltages than the conventional circuit. Especially, the proposed circuit has more excellent pulse-width matching of set and reset signals than the conventional circuit. Also, the proposed pulse generator is prevented from fault operations using a logic gate. Dead time and pulse-width of the proposed circuit are typical 250 ns, respectively. The variation ratio is 68%(170 ns) of maximum over variation of processes and supply voltages. The proposed circuit is designed using $1\;{\mu}m$ 650 V BCD (Bipolar, CMOS, DMOS) process parameter, and the simulations are carried out using Spectre simulator of Cadence corporation.

• 대한전자공학회논문지SD
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• 제42권3호
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• pp.43-50
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• 2005

본 논문에서는 다운 디지털 회로(DLC)를 이용하여 4치 논리 게이트를 설계하였고, 이들 게이트를 이용하여 동기식 4치 up/down 카운터를 제안하였다. 제안된 카운터는 T-type 4치 플립플롭과 $2\times1$ 임계-t 멀티플렉서로 이루어져 있고, T-type 4치 플립플롭은 D-type 4치 플립플롭과 4치 논리 게이트들(모듈러-4 가산 게이트, 4치 인버터, 항등 셀, $4\times1$ 멀티플렉서)로 구성되어 있다. 이 카운터의 모의실험 결과는 10[ns]의 지연시간과 8.48[mW]의 전력소모를 보여준다. 또한 다치논리 회로로 설계된 카운터는 상호결선과 칩 면적의 감소뿐만 아니라 디지트 확장의 용이함의 이점을 가진다.

• International Journal of Fuzzy Logic and Intelligent Systems
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• 제2권2호
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• pp.146-152
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• 2002

Mold level control has been a major control task for continuous casting plants. The system involves nonlinearities such as stick-slip friction in the sliding gate, time-delay, friction force variations between molten steel and the inner wall of mold, and nozzle logging/unclogging. These complex problems should be solved to control mold level for steel cast. In this paper, we propose a neural fuzzy mold level control technique for solving these complex problems and give experiment studies to show the mold level control in continuous casting process.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1987년도 전기.전자공학 학술대회 논문집(II)
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• pp.1481-1484
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• 1987

The ALU of CMOS microcomputer have been designed with the 3um design rule for CMOS polysilicon gate and Its cells were layed out. The operation of circuits were simulated with EDAS_P. The widths and lengths of gates In the circuit were determined using SPlCE. The carry delay of the ALU was Improved by Manchester carry method. The results of logic and circuit simulation were in good agreement with expected circuit characteristics.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2001년도 합동 추계학술대회 논문집 정보 및 제어부문
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• pp.165-168
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• 2001

This paper presents a design of a divide unit supporting IEEE-754 floating point standard single-precision with 32-bit word length. Its functions have been verified with ALTERA MAX PLUS II tool. For a high-speed division operation, the radix-4 non-restoring algorithm has been applied and CLA(carry-look -ahead) adders has been used in order to improve the area efficiency and the speed of performance for the fraction division part. The prevention of the speed decrement of operations due to clocking has been achieved by taking advantage of combinational logic. A quotient select block which is very complicated and significant in the high-radix part was designed by using P-D plot in order to select the fast and accurate quotient. Also, we designed all division steps with Gate-level which visualize the operations and delay time.

• 전자공학회논문지B
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• 제32B권11호
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• pp.1434-1444
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• 1995

Current test has recently been known to be a promising testing method in CMOS VLSI because conventional voltage test can not make sure of the complete detection of bridging, gate-oxide shorts, stuck-open faults and etc. This paper presents a new BIC(built-in current sensor) for the internal current test in CMOS logic circuit. A single phase clock is used in the BIC to reduce the control circuitry of it and to perform a self- testing for a faulty current. The BIC is designed to detect the faulty current at the end of the clock period, so that it can test the CUT(circuit under test) with much longer critical propagation delay time and larger area than conventional BICs. The circuit is composed of 18 devices and verified by using the SPICE simulator.

• 센서학회지
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• 제33권3호
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• pp.147-151
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• 2024

The importance of Wireless Sensor Networks is becoming more evident owing to their practical applications in various areas. However, the energy problem remains a critical barrier to the progress of WSNs. By reducing the energy consumed by the sensor nodes that constitute WSNs, the performance and lifespan of WSNs will be enhanced. In this study, we introduce an energy-efficient ternary modulator that employs multi-threshold CMOS for logic conversion. We optimized the design with a low-power ternary gate structure based on a pass transistor using the MTCMOS process. Our design uses 71.69% fewer transistors compared to the previous design. To demonstrate the improvements in our design, we conducted the HSPICE simulation using a CMOS 180 nm process with a 1.8V supply voltage. The simulation results show that the proposed ternary modulator is more energy-efficient than the previous modulator. Power-delay product, a benchmark for energy efficiency, is reduced by 97.19%. Furthermore, corner simulations demonstrate that our modulator is stable against PVT variations.

• 전자공학회논문지
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• 제53권4호
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• pp.37-47
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• 2016

광폭입력함수 전용 멀티플렉서가 슬라이스 구조에 포함되는 상용 FPGA의 현실적 제약 조건을 학계의 대표적 논리 표현 방식인 AIG (And-Inverter Graph)를 근간으로 개발된 FPGA 매핑 알고리즘에 적용하였다. AIG를 LUT (Look-Up Table)으로 매핑할 때 중간 구조로서 컷을 열거하는 데 이들 중에서 멀티플렉서를 인식해 낸 후 이들이 매핑될 때 지연 시간 및 면적을 복잡도 증가 없이 계산하도록 하였다. 이 때 트리 형성 전제 조건인 대칭성과 단수 제약 요건도 검사하도록 하였다. 또한, 멀티플렉서 트리의 루트 위치를 RTL 코드에서 찾아내고 이를 보조 출력 형태로 AIG에 추가하도록 하였다. 이 위치에서 섀넌확장을 통해 멀티플렉서 트리 구조를 의도적으로 합성한 후 최적 AIG에 겹치도록 하는 접근 방법을 최초로 제안하였다. 이때 무손실 합성을 가능하게 하는 FRAIG 방식이 응용되었다. 두 가지 프로세서에 대해 제안된 접근 방법과 기법들을 적용하여 약 13~30%의 면적 감소 및 최대 32%까지의 지연 시간 단축을 달성하였다. AIG 트리에 특정 구조를 의도적으로 주입시키는 접근 방법은 향후 캐리 체인 등에 확장 적용하는 연구가 진행될 것이다.