• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.31-32
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• 2010

In our previous reports [1-3], electron transport for the switching and memory devices using alkyl thiol-tethered Ru-terpyridine complex compounds with metal-insulator-metal crossbar structure has been presented. On the other hand, among organic memory devices, a memory based on the OFET is attractive because of its nondestructive readout and single transistor applications. Several attempts at nonvolatile organic memories involve electrets, which are chargeable dielectrics. However, these devices still do not sufficiently satisfy the criteria demanded in order to compete with other types of memory devices, and the electrets are generally limited to polymer materials. Until now, there is no report on nonvolatile organic electrets using nano-interfaced organic monomer layer as a dielectric material even though the use of organic monomer materials become important for the development of molecularly interfaced memory and logic elements. Furthermore, to increase a retention time for the nonvolatile organic memory device as well as to understand an intrinsic memory property, a molecular design of the organic materials is also getting important issue. In this presentation, we report on the OFET memory device built on a silicon wafer and based on films of pentacene and a SiO2 gate insulator that are separated by organic molecules which act as a gate dielectric. We proposed push-pull organic molecules (PPOM) containing triarylamine asan electron donating group (EDG), thiophene as a spacer, and malononitrile as an electron withdrawing group (EWG). The PPOM were designed to control charge transport by differences of the dihedral angles induced by a steric hindrance effect of side chainswithin the molecules. Therefore, we expect that these PPOM with potential energy barrier can save the charges which are transported to the nano-interface between the semiconductor and organic molecules used as the dielectrics. Finally, we also expect that the charges can be contributed to the memory capacity of the memory OFET device.[4]

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.48 no.12
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• pp.1005-1012
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• 2020

Avionics systems that use the PCI-Express bus unfortunately cannot use at least one I/O device if the bus fails, because the I/O device is connected to CPU through only one PCI-Express channel. This paper presents a fault-tolerant architecture of the PCI-Express bus for avionics systems, which tolerates one channel failure with help of the other redundant channel that has not been failed. In this architecture, each redundant PCI-Express channel connects a corresponding port of CPU to each switch logic of channels to provide each I/O device through a switched fault-tolerant channel. This paper includes the results of experimentation to show that the architecture detects the faulty condition in real time and switches the channel to the other redundant channel which has not been failed, when the architecture meets a failure.

• International Journal of Fuzzy Logic and Intelligent Systems
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• v.14 no.2
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• pp.122-129
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• 2014

Effective information gathering and retrieval of the most relevant web documents on the topic of interest is difficult due to the large amount of information that exists in various formats. Current information gathering and retrieval techniques are unable to exploit semantic knowledge within documents in the "big data" environment; therefore, they cannot provide precise answers to specific questions. Existing commercial big data analytic platforms are restricted to a single data type; moreover, different big data analytic platforms are effective at processing different data types. Therefore, the development of a common big data platform that is suitable for efficiently processing various data types is needed. Furthermore, users often possess more than one intelligent device. It is therefore important to find an efficient preference profile construction approach to record the user context and personalized applications. In this way, user needs can be tailored according to the user's dynamic interests by tracking all devices owned by the user.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2010.11a
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• pp.18-20
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• 2010

본 논문에서는 3차원 모니터를 시청하는 시청자의 위치를 추적한 후 시청위치에 따라 다른 시점의 영상을 제공하는 시스템을 제안한다. 본 시스템은 센서들의 신호를 제어하는 CPU, 3개의 초음파센서, 1개의 PIR(Passive infrared radiation)센서, 센서별 신호를 분기해주는 PLD(programmable logic device)로 구성되어 있다. 3개의 초음파 센서를 이용해 20개의 탐색구역 내에 있는 시청자의 정확한 위치를 추적한다. 시스템을 구현한 결과 전방 5m, 좌우 3m의 탐색범위 내에서 시청자의 위치를 정확히 추적하여 해당 시점의 영상을 디스플레이 하였다.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.585-588
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• 2004

This paper describes design and verification of the motion estimation and compensation unit using full search algorithm. Video processor is the key device of video communication systems. Motion estimation is the key module of video processor. The technologies of motion estimation and compensation unit are the core technologies for wireless video telecommunications system, portable multimedia systems. In this design, Verilog simulator and logic synthesis tools are used for hardware design and verification. In this paper, motion estimation and compensation unit are designed using FPGA, coded in Verilog HDL, and simulated and verified using Xilinx FPGA.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.655-658
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• 2005

Due to reduced device sizes and threshold voltages, leakage current becomes an important issue in CMOS design. In a CMOS combinational logic circuit, the leakage current in the standby state depends on the state of the inputs and thus can be minimized by applying an optimal input when the circuit is idling. In this paper, we present a New Input Vector Control algorithm, called Leakage Minimization by Input vector Control (LMIC) for minimal leakage power. This algorithm finds the minimal leakage vector and reduces leakage current up to 22.% on the average, for TSMC 0.18um process parameters. Minimal leakage vectors are very useful in reducing leakage currents in standby mode of operation.

• International Journal of Advanced Culture Technology
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• v.2 no.2
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• pp.7-10
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• 2014

In order to develop smart grid communications infrastructure, a high level of interconnectivity and reliability among its nodes is required. Sensors, advanced metering devices, electrical appliances, and monitoring devices, just to mention a few, will be highly interconnected allowing for the seamless flow of data. Reliability and security in this flow of data between nodes is crucial due to the low latency and cyber-attacks resilience requirements of the Smart Grid. In particular, Artificial Intelligence techniques such as Fuzzy Logic, Bayesian Inference, Neural Networks, and other methods can be employed to enhance the security gaps in conventional IDSs. A distributed FPGA-based network with adaptive and cooperative capabilities can be used to study several security and communication aspects of the smart grid infrastructure both from the attackers and defensive point of view. In this paper, the vital issue of security in the smart grid is discussed, along with a possible approach to achieve this by employing FPGA based Radial Basis Function (RBF) network intrusion.

• Proceedings of the IEEK Conference
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• 2000.09a
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• pp.501-504
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• 2000

근본적으로 방대한 양의 실시간 연산을 요구하는 영상 신호처리, 소나, 레이다와 같은 시스템에서는 시스템의 성능을 최대화하기 위해 병렬 신호처리 시스템의 사용이 불가피하다. 본 논문은 방대한 양의 데이터를 실시간으로 처리할수 있는 병렬 신호처리보드를 설계 및 구현하였다. 이 보드는 DSP칩간의 통신과 보드간의 통신이 가능하며, DSP칩이 마스터가 되어 EMIF(External Memory Interface Port)포트를 통해 다른 DSP칩의 지역메모리를 액세스 할수 있다. 또한 외부의 호스트 프로세서가 보드 내의 DSP칩에 프로그램을 다운로딩 할수 있다. 보드간의 통신은 PCI 버스를 통하여 이루어지며, DSP칩간의 통신과 DSP칩과 그의 지역메모리와의 통신은 지역버스를 통해 직접적으로 이루어진다. 보드에서 가장 핵심인 DSP-to-PCI제어기는 하드웨어 언어인 VHDL로 설계하였으며, 시뮬레이션 환경은 Synopsys ＆ ALTERA MaxplusⅡ를 사용하여 검증하였으며, 최종적으로 CPLD(Complex Programable Logic Device)칩을 사용하여 구현하였다.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 2003.09a
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• pp.58-61
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• 2003

This paper proposes e-Learning environments far digital circuit experiment. The e-Learning environments are implemented as a WBT system that includes the circuits monitoring system and the students management system. In the WBT client-server system, the instructor represents the server and students represent clients. The client computers are equipped with a digital circuit training board and connected to the server on the World Wide Web. The training board consists of a Programmable Logic Device (PLD) and measuring instruments. The instructor can reconfigure the PLD with various circuit designs from the server so that students can investigate signals from the training board. The instructor can monitor the progress of the students using Joint Test Action Grouo(JTAG) technology. We implement the WBT system and a courseware fo digital circuits and evaluation the environments.

• Journal of the Korean Institute of Intelligent Systems
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• v.7 no.1
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• pp.27-33
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• 1997

This project is dedicated to the elaboration of a man-machine system for monitoring the non spread of nuclear weapons, technologies, raw materials. The main purpose of such a system depends on the customer requirements and may be : - control of non proliferation of nuclear technologies, especially those that can be used to manufacture a nuclear explosive device; - the appraisal of the possibility of production of nuclear weapons by a certain country on the basic of its intellectual and scientific-technical potential, its raw material resources, its export-import potential and other parameters.