Journal of the Korean Society for Aeronautical & Space Sciences (한국항공우주학회지)

The Korean Society for Aeronautical and Space Sciences (한국항공우주학회)
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A Fault-Tolerant Architecture of PCI-Express Bus for Avionics Systems

항공전자 시스템을 위한 PCI-Express 버스의 결함감내 구조

  • Received : 2020.01.08
  • Accepted : 2020.10.20
  • Published : 2020.12.01
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Abstract

Avionics systems that use the PCI-Express bus unfortunately cannot use at least one I/O device if the bus fails, because the I/O device is connected to CPU through only one PCI-Express channel. This paper presents a fault-tolerant architecture of the PCI-Express bus for avionics systems, which tolerates one channel failure with help of the other redundant channel that has not been failed. In this architecture, each redundant PCI-Express channel connects a corresponding port of CPU to each switch logic of channels to provide each I/O device through a switched fault-tolerant channel. This paper includes the results of experimentation to show that the architecture detects the faulty condition in real time and switches the channel to the other redundant channel which has not been failed, when the architecture meets a failure.

PCI-Express 버스를 적용하는 항공전자 시스템은 CPU와 입출력 장치를 하나의 채널만을 사용하여 연결하기 때문에, 불행하게도 그 채널에 고장이 발생하면 적어도 하나의 입출력 장치를 사용할 수 없게 되는 문제가 있다. 본 논문은 항공전자 시스템을 위한 PCI-Express 버스의 결함감내 구조를 제시하기 위해서, PCI-Express 채널을 이중화하여 하나의 채널에 고장이 발생하여도 고장이 발생하지 않은 다른 채널을 통해 여전히 정상적으로 기능하는 버스 구조를 제시한다. 논문에서 제시하는 버스 구조는 두 개의 CPU port에서 출력된 이중적 PCI-Express 버스 신호를 각각의 switch 회로에 입력되게 하고, 이 회로가 각 입출력 장치에 결함을 감내하도록 선택된 독립된 버스 채널을 제공하게 한다. 본 논문에서는 제시하는 버스 구조를 구현 및 실험하여 하나의 PCI-Express 버스에 고장이 발생하면, 그 고장 상황을 실시간으로 감지되고, 고장이 발생하지 않은 다른 버스로 채널을 전환되어 정상적으로 통신이 수행되는 것을 보인다.

Keywords

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