• Proceedings of the KIEE Conference
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• 1996.07b
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• pp.1122-1124
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• 1996

Depth between the robot and the target is an essential information in the robot control. However, in case of eye-in-hand robot with one camera, it is not easy to get an accurate depth information in real-time. In this paper, the techniques of depth-from-motion and depth-from-focus are combined to accomplish the real-time requirement. Integration of the two approaches are accomplished by appropriate use of confidence factors which are evaluated by fuzzy rules. Also a fuzzy logic based calibration technique is proposed.

• The Transactions of the Korean Institute of Power Electronics
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• v.8 no.5
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• pp.381-388
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• 2003

In this paper, the IED(Intelligent Electronic Devices) with the consideration of harmonic problems is discussed, With significant development of power electronics technology, the proliferation of a nonlinear load has more deteriorated power quality, As continuous harmonic current makes for a shortening lifetime, overheat and abnormal operation, it should be considered to improve these problems. However, the conventional digital protective relay which eliminates harmonic elements with orthogonal filter has a defect on actually implementation. The prototype IED is constructed with Digital Signal Processor(TMS320C32) and Complex Programmable Logic Device. According to the experiment and simulation results, it is proved that the proposed system has good performance of measuring harmonic factors and protecting electrical equipment.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2003.09a
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• pp.109-119
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• 2003

o In order to start SIP Project .Marketing (& ASIC team) should present biz planning, schedule, device/SIP specs., in SIP TFT prior to request SIP development for package development project. .In order to prevent (PCB) revision, test, burn-in, & quality strategy should be fixed by SIP TFT (PE/Test, QA) prior to request for PKG development. .Target product price/cost, package/ test cost should be delivered and reviewed. o Minimum Information for PCB Design, Package Size, and Cost .(Required) package form factor: size, height, type (BGA, QFP), Pin count/pitch .(Estimated) each die size including scribe lane .(Estimated) pad inform. : count, pitch, configuration(in-line/staggered), (open) size .(Estimated) each device (I/O & Core) power (especially for DRAM embedded SIP) .SIP Block diagram, and net-list using excel sheet format o Why is the initial evaluation important\ulcorner .The higher logic power resulted in spec. over of DRAM Tjmax. This caused business drop longrightarrow Thermal simulation of some SIP product is essential in the beginning stage of SIP business planning (or design) stage. (i.e., DRAM embedded SIP) .When SIP is developed using discrete packages, the I/O driver Capa. of each device may be so high for SIP. Since I/O driver capa. was optimized to discrete package and set board environment, this resulted in severe noise problem in SIP. longrightarrow In this case, the electrical performance of product (including PKG) should have been considered (simulated) in the beginning stage of business planning (or design).

• Journal of information and communication convergence engineering
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• v.20 no.3
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• pp.166-173
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• 2022

Recently, studies have been conducted on intelligent transportation systems (ITS) that provide safety and convenience to humans. Systems that compose the ITS adopt architectures that applied the cloud computing which consists of a high-performance general-purpose processor or graphics processing unit. However, an architecture that only used the cloud computing requires a high network bandwidth and consumes much power. Therefore, applying edge computing to ITS is essential for solving these problems. In this paper, we propose an edge artificial intelligence (AI) device based ITS. Edge AI which is applicable to various systems in ITS has been applied to license plate recognition. We implemented edge AI on a field-programmable gate array (FPGA). The accuracy of the edge AI for license plate recognition was 0.94. Finally, we synthesized the edge AI logic with Magnachip/Hynix 180nm CMOS technology and the power consumption measured using the Synopsys's design compiler tool was 482.583mW.

• Journal of the Korean Society for Aviation and Aeronautics
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• v.32 no.2
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• pp.11-19
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• 2024

Flight simulators are crucial devices for aircraft piloting training and simulation, requiring regular inspections to maintain performance and operational quality. This study explores the development of an automated inspection system for flight simulators to automate quality inspections of control loading systems (CLS). While quality inspection of the control loading system (CLS) is essential for flight simulators, manual inspections are common practice. To address this, we developed an Auto Qualification Test Guide (Auto QTG) using artificial control logic and sensor data and applied it to the militarily simulator. Experimental results demonstrate that Auto QTG successfully automates quality inspections of CLS, enhancing accuracy and efficiency. This automated inspection system is expected to contribute to improving the operation and maintenance of flight simulators.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.21 no.5
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• pp.59-69
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• 2011

Since power analysis attack which uses a characteristic that power consumed by crypto device depends on processed data has been proposed, many logics that can block these correlation originally have been developed. DRP logic has been adopted by most of logics maintains power consumption balanced and reduces correlation between processed data and power consumption. However, semi-custom design is necessary because recently design circuits become more complex than before. This design method causes unbalanced design pattern that makes DRP logic consumes unbalanced power consumption which is vulnerable to power analysis attack. In this paper, we have developed new logic style which adds another discharge phase to discharge two output nodes at the same time based on DyCML to remove this unbalanced power consumption. Also, we simulated 1bit fulladder to compare proposed logic with other logics to prove improved performance. As a result, proposed logic is improved NED and NSD to 60% and power consumption reduces about 55% than any other logics.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.8C
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• pp.1210-1217
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• 2004

LILI-II stream cipher is an upgraded version of the LILI-128, one of candidates in NESSIE. Since the algorithm is a clock-controlled, the speed of the keystream data is degraded structurally in a clock-synchronized hardware logic design. Accordingly, this paper proposes a 4-bit parallel LFSR, where each register bit includes four variable data routines for feedback or shifting within the LFSR. furthermore, the timing of the proposed design is simulated using a Max+plus II from the ALTERA Co., the logic circuit is implemented for an FPGA device (EPF10K20RC240-3), and apply to the Lucent ASIC device (LV160C, 0.13${\mu}{\textrm}{m}$ CMOS ＆ 1.5v technology), and it could achieve a throughput of about 500 Mbps with a 0.13${\mu}{\textrm}{m}$ semiconductor for the maximum path delay below 1.8㎱. Finally, we propose the m-parallel implementation of LILI-II, throughput with 4, 8 or 16 Gbps (m=8, 16 or 32).

• Journal of the Korea Academia-Industrial cooperation Society
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• v.4 no.3
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• pp.301-306
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• 2003

We have designed embedded web server system and ported Linux operating system version 2.4.1 at our system. And then We implemented to control and monitor widely separated hardware. Web server is the Boa web server with General Public License. We designed for this system using of Cirrus logic's EP7312 ARM core base processor and connecting input and output device at GPIO port of EP7312. Device driver of General purpose I/O for Linux OS is designed. And then the application program controlling driver is implemented to use of common gate interface C language. User is available to control and monitor at client PC. This method have benefit to reduce the Expenditure of hardware design and development time against PC base system and have various and capacious application against firmware base system.

• Journal of Astronomy and Space Sciences
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• v.14 no.2
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• pp.259-268
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• 1997

We present the development process of a prototype CCD imaging system which is being built at Korea Astronomy Observatory(KAO) for astronomical applications. The CCD imaging system requires very low noise and high stability characteristics and is widely used for astronomical purposes from infrared to ultraviolet wavelength regions. However its system design, particularly for the controller design technique, as heart of the system, is not secured in Korea so far. The prototype electronics developed in this study consists of a signal chip controller which was implemented in an EPLD(Erasable Programable Logic Device) and an analog driver, a video processor with a LN2 cooling cryostat. A PC system was employed to control the whole system and to store the image data considering compatibility of the system. We have successfully obtained the first image in the laboratory with the prototype of this imaging system, and an image of the M15 at Sobaeksan Astronomy Observatory.

• KEPCO Journal on Electric Power and Energy
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• v.6 no.3
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• pp.253-257
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• 2020

The local information processing devices are devices that process information by converting voltage, current, and digital electric signals from legacy-type power facility into IEC 61850 based data. It acquires and processes the operation information of legacy-type power facility, performs control of power facility, and interlock function using internal logic. In particular, the time to convert data to process input and output information for a device is important because a number of protection relay input and output signals are handled by only one device. This paper introduces test methods and cases for measuring IEC 61850 communication function and input/output data conversion time of local information processing device.