• 전자공학회논문지A
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• 제32A권4호
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• pp.93-102
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• 1995

This paper introduces a general purpose Associative Processor(AP) which is very efficient for search-oriented applications. The proposed architecture consists of three main functional blocks: Content-Addressable Memory(CAM) arry, row logic, and control section. The proposed AP is a Single-Instruction, Multiple-Data(SIMD) device based on a CAM core and an array of high speed processors. As an application for the proposed hardware, we present a parallel algorithm to solve a global routing problem in the layout process utilizing the processing capabilities of a rudimentary logic and the selective matching and writing capability of CAMs, along with basic algorithms such a minimum(maximum) search, less(greater) than search and parallel arithmetic. We have focused on the simultaneous minimization of the desity of the channels and the wire length by sedking a less crowded channel with shorter wire distance. We present an efficient mapping technique of the problem into the CAM structure. Experimental results on difficult examples, on randomly generated data, and on benchmark problems from MCNC are included.

• 한국CDE학회논문집
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• 제18권1호
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• pp.21-27
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• 2013

Presented in the paper is a log data based modeling method for effective construction of a virtual plant model which can be used for the virtual PLC (Programmable Logic Controller) simulation. For the PLC simulation, the corresponding virtual plant, consisting of virtual devices, is required to interact with the input and output symbols of a PLC. In other words, the behavior of a virtual device should be the same as that of the real device. Conventionally, the DEVS (Discrete Event Systems Specifications) formalism has been used to represent the behavior a virtual device. The modeling using DEVS formalism, however, requires in-depth knowledge in the simulation area, as well as the significant amount of time and efforts. One of the key ideas of the proposed method is to generate a plant model based on the log data obtained from the production system. The proposed method is very intuitive, and it can be used to generate the full behavior model of a virtual device. The proposed approach was applied to an AGV (Automated Guided Vehicle).

• 대한전자공학회논문지SD
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• 제43권12호
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• pp.40-46
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• 2006

본 연구에서는 GaAs/AlGaAs 구조의 수직 구조 레이저 - 완전 공핍 광 싸이리스터를 제작하여, 광 논리 및 광 스위칭 시스템에 응용할 수 있는, 광 AND- 와 OR- 게이트를 구현하였고, 그 특성을 측정, 분석하였다. 제작된 단일 소자 타입의 광 싸이리스터는 하나의 소자에서 간단한 기준 스위칭 전압의 변화만으로 광 AND 와 OR 게기트를 모두 구현할 수 있다는 장점을 갖는다. 활성층 위, 아래에 1/4 파장 거울층 구조를 채택하고, 선택적 산화공법을 이용하여 0.65 mA의 낮은 문턱전류 값을 얻었고, 50dB 이상의 높은 온/오프 대비를 보였으며, 높은 광 출력 효율과 입력 광 신호에 대한 높은 선택도를 얻을 수 있었다. 제작된 광 싸이리스터는 실험적으로 S자형의 전류-전압 특성곡선을 얻었고, 빛의 세기가 증가함에 따라 스위칭 전압이 5.20V에서 1.90V로 현저히 줄어드는 것을 확인하였다

• JSTS:Journal of Semiconductor Technology and Science
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• 제6권3호
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• pp.154-161
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• 2006

This paper describes the new types of ngative differential resistance (NDR) IC applications which use a monolithic quantum-effect device technology based on the RTD/HBT heterostructure design. As a digital IC, a low-power/high-speed MOBILE (MOnostable-BIstable transition Logic Element)-based D-flip flop IC operating in a non-return-to-zero (NRZ) mode is proposed and developed. The fabricated NRZ MOBILE D-flip flop shows high speed operation up to 34 Gb/s which is the highest speed to our knowledge as a MOBILE NRZ D-flip flop, implemented by the RTD/HBT technology. As an analog IC, a 14.75 GHz RTD/HBT differential-mode voltage-controlled oscillator (VCO) with extremely low power consumption and good phase noise characteristics is designed and fabricated. The VCO shows the low dc power consumption of 0.62 mW and good F.O.M of -185 dBc/Hz. Moreover, a high-speed CML-type multi-functional logic, which operates different logic function such as inverter, NAND, NOR, AND and OR in a circuit, is proposed and designed. The operation of the proposed CML-type multi-functional logic gate is simulated up to 30 Gb/s. These results indicate the potential of the RTD based ICs for high speed digital/analog applications.

• Journal of Information Display
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• 제5권1호
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• pp.28-33
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• 2004

A high voltage NMOSFET is proposed to drive top emission organic light emitting device (OLED) used in the organic electroluminescent (EL) display on the single crystal silicon substrate. The high voltage NMOSFET can be fabricated by utilizing a simple layout technique with a standard CMOS logic process. It is clearly shown that the maximum supply voltage ($V_{DD}$) required for the pixel-driving transistor could reach 45 V through analytic and experimental methods. The high voltage NMOSFET was fabricated by using a standard 1.5 ${\mu}m$, 5 V CMOS logic process. From the measurements, we confirmed that the high voltage NMOSFET could sustain the excellent saturation characteristic up to 50 V without breakdown phenomena.

• JSTS:Journal of Semiconductor Technology and Science
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• 제10권2호
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• pp.134-142
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• 2010

A comparative study on the trade-off between the drive current and the total gate capacitance in double-gate (DG) and triple-gate (TG) FinFETs is performed by using 3-D device simulation. As the first result, we found that the optimum ratio of the hardmask oxide thickness ($T_{mask}$) to the sidewall oxide thickness ($T_{ox}$) is $T_{mask}/T_{ox}$=10/2 nm for the minimum logic delay ($\tau$) while $T_{mask}/T_{ox}$=5/1~2 nm for the maximum intrinsic gate capacitance coupling ratio (ICR) with the fixed channel length ($L_G$) and the fin width ($W_{fin}$) under the short channel effect criterion. It means that the TG FinFET is not under the optimal condition in terms of the circuit performance. Second, under optimized $T_{mask}/T_{ox}$, the propagation delay ($\tau$) decreases with the increasing fin height $H_{fin}$. It means that the FinFET-based logic circuit operation goes into the drive current-dominant regime rather than the input gate load capacitance-dominant regime as $H_{fin}$ increases. In the end, the sensitivity of $\Delta\tau/{\Delta}H_{fin}$ or ${{\Delta}I_{ON}}'/{\Delta}H_{fin}$ decreases as $L_G/W_{fin}$ is scaled-down. However, $W_{fin}$ should be carefully designed especially in circuits that are strongly influenced by the self-capacitance or a physical layout because the scaling of $W_{fin}$ is followed by the increase of the self-capacitance portion in the total load capacitance.

• 실천공학교육논문지
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• 제10권1호
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• pp.49-56
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• 2018

비전공 학부생을 대상으로 다양한 방식의 SW 교육이 대학별로 운영되고 있다. 그리고 대부분 컴퓨팅적 사고를 교육하는 데 초점을 맞추고 있다. 이러한 컴퓨팅 교육에 이어서 학생들마다 창의적인 컴퓨팅 산출물을 구현하고 평가하는 교육 방식이 필요하다. 본 논문에서는 창의적 컴퓨팅 산출물 기반 SW교육을 실현하는 한 가지 방안을 제안한다. 이를 위해 학생들이 디지털논리회로 장치를 창의적으로 구현하고, 이 장치의 기능을 구현하는 SW알고리즘을 디자인하는 교육방법을 제안한다. 제안한 교육 방법에서는 아두이노 보드를 사용한 간단한 LED 논리회로를 예로 들어 교육한다. 학생들은 2변수 논리회로 출력장치 두 쌍을 창의적으로 설계 및 구현하고, 구현한 장치의 패턴을 나타내는 알고리즘을 다양한 형태로 설계한다. 그리고 입력장치를 이용한 기능 확장 및 확장된 알고리즘을 설계한다. 제안한 교육방법을 적용하면, 비전공 학생들이 창의적 컴퓨팅 산출물 제작을 통해 알고리즘 설계의 개념과 필요성을 습득하는 성과를 얻을 수 있다.

• International Journal of Fuzzy Logic and Intelligent Systems
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• 제5권3호
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• pp.230-245
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• 2005

In this paper, we develop a gesture-based input device equipped with accelerometers and gyroscopes. The sensors measure the inertial measurements, i.e., accelerations and angular velocities produced by the movement of the system when a user is inputting gestures on a plane surface or in a 3D space. The gyroscope measurements are integrated to give orientation of the device and consequently used to compensate the accelerations. The compensated accelerations are doubly integrated to yield the position of the device. With this approach, a user's gesture input trajectories can be recovered without any external sensors. Three versions of motion tracking algorithms are provided to cope with wide spectrum of applications. Then, a Bayesian network based recognition system processes the recovered trajectories to identify the gesture class. Experimental results convincingly show the feasibility and effectiveness of the proposed gesture input device. In order to show practical use of the proposed input method, we implemented a prototype system, which is a gesture-based remote controller (Magic Wand).

• 한국자기학회:학술대회 개요집
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• 한국자기학회 2006년도 임시총회 및 하계학술연구발표회
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• pp.57-57
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• 2006

• 전력전자학회:학술대회논문집
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• 전력전자학회 2000년도 전력전자학술대회 논문집
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• pp.641-644
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• 2000

Recently As the performance of the personal computer has been improving rapidly lots of research for the pc-based numerical computer actively progress in an easy repair maintenance and improving the performance with less cost. This paper presents the design using complex programmable logic device(CPLD). The CPU of Motion Controller that function as the real time control of the independent multi-axis motion the error-detect module and external I/O control made use of 80C196KC, In this paper The PC-NC effectively distributed to the load of NCK(numerical computer kernel) and have the advantage of high speed and precision.