A Study on the Design of PLL for Improving of Characteristics of Locking Time and Jitter (Locking Time과 Jitter 특성의 개선을 위한 PLL 설계에 관한 연구)
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- Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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- 2003.07b
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- pp.1188-1191
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- 2003