• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.11a
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• pp.7-10
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• 2003

ABS interface IC for automobiles was designed and their electrical properties were investigated. The voltage regulator was designed to operate in the temperature range from $-20^{\circ}\;to\;120^{\circ}C$ for automobile environment. ABS and brake signal were separated using the duty factor of same frequency or different frequencies. UVLO circuit and constant current circuit were applied for the elimination of noise.

• Proceedings of the KIEE Conference
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• 2000.11b
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• pp.372-374
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• 2000

This paper presents a study on the indirect FOC (field oriented control) of induction motor using TMS320F240. This DSP has become possible to design and implement a highly efficient and accurate AC induction drive control. This paper describes a pulse width modulator based on the voltage space vectors technique that accepts voltage demands in dq coordinates and generates three-phase PWM waveforms to drive a variable frequency voltage-source inverter. The Current Model lock is added to generate the rotor flux angular speed.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.4
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• pp.506-517
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• 2015

This paper presents a 1.248 Gb/s - 2.918 Gb/s low-power receiver MIPI-DigRF M-PHY with a fully digital frequency detection loop. MIPI-DigRF M-PHY should be operated in a very short training time which is $0.01{\mu}s$ the for HS-G2B mode. Because of this short SYNC pattern, clock and data recovery (CDR) should have extremely fast locking time. Thus, the quarter rate CDR with a fully digital frequency detection loop is proposed to implement a fast phase tracking loop. Also, a low power CDR architecture, deserializer and voltage controlled oscillator (VCO) are proposed to meet the low power requirement of MIPI-DigRF M-PHY. This chip is fabricated using a $0.11{\mu}m$ CMOS process, and the die area is $600{\mu}m{\times}250{\mu}m$. The power consumption of the receiver is 16 mW from the supply voltage of 1.1 V. The measured lock time of the CDR is less than 20 ns. The measured rms and peak jitter are $35.24ps_{p-p}$ and $4.25ps_{rms}$ respectively for HS-G2 mode.

• Journal of Power Electronics
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• v.18 no.1
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• pp.234-250
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• 2018

This paper presents a new load sharing control for use between paralleled three-phase inverters in an islanded microgrid based on the online line impedance estimation by the use of a Kalman filter. In this study, the mismatch of power sharing when the line impedance changes due to temperature, frequency, significant differences in line parameters and the requirements of the Plug-and-Play mode for inverters connected to a microgrid has been solved. In addition, this paper also presents a new droop control method working with the line impedance that is different from the traditional droop algorithm when the line impedance is assumed to be pure resistance or pure inductance. In this paper, the line impedance estimation for parallel inverters uses the minimum square method combined with a Kalman filter. In addition, the secondary control loops are designed to restore the voltage amplitude and frequency of a microgrid by using a combined nominal value SOGI-PLL with a generalized integral block and phase lock loop to monitor the exact voltage magnitude and frequency phase at the PCC. A control model has been simulated in Matlab/Simulink with three voltage source inverters connected in parallel for different ratios of power sharing. The simulation results demonstrate the accuracy of the proposed control method.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 1999.11a
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• pp.161-166
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• 1999

The global trends of mobile communication system is moving toward digitizing, high-speed and large-capacity. Also, to utilize the limited frequency-resource efficiently, spread spectrum system is a mainstream. In this study we are concerning with the fast frequency-hopping system. Instead of the PLL with many problems such as phase-noise, we used the DDS is popular in these days minimizes the disadvantage of PLL. In the case the FFH system is designed using the PLL, it is difficult to be satisfied of the design conditions such as RF badwidth and the settling time of PLL, and it has limitation because of complex circuit by using the balanced modulator. In this study, we evaluated the performance in order to design the FFH system using the DDS. The system that has the improvement of error rate, 1Mhps hopping rate and 5MHz RF bandwidth is designed and evaluated.

• Journal of the Korean Society for Nondestructive Testing
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• v.14 no.4
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• pp.237-243
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• 1995

We have studied methods of detecting attenuation of solid materials such as silicon wafer and piezoelectric $LiTaO_3$ by means of optical probing techniques. We have performed measurements of surface acoustic waves(SAW) generated from 90 degree wedge type transducer and also from inter-digital transducers(IDT). SAW of 20.0 MHz was generated on a silicon wafer from the 90 degree wedge type transducer and those of 20.8 and 14.5 MHz are generated on a $LiTaO_3$ from the IDT. Then any surface-corrugation resulted from the above SAW was investigated by He-Ne laser beams. We projected laser beams, which were modulated by an optical chopper, on the SAW of the same frequency and then measured the scattered beam by the lock-in amplifier. We modulated and synchronized both SAW and the incident laser beam as well as the phase sensitive detector(PSD) to the same frequency in order to simplify our measurement system. We obtained the attenuation coefficients of SAW to be $0.62{\sim}0.75dB/mm$(from IDT1, 20.8 MHz), and $0.60{\sim}0.72dB/mm$(from IDT2, 14.5 MHz), $0.83{\sim}1.28dB/mm$(from the wedge type), respectively.

• Journal of IKEEE
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• v.14 no.1
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• pp.65-74
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• 2010

The Digital TV(DTV) standard has ushered in a new era in TV broadcasting and raised a great demand for DTV tuners. There are many challenges in designing a DTV tuner, of which the most difficult part is the frequency synthesizer. This paper presents the design of a frequency synthesizer for DTV Tuners in a $0.18{\mu}m$ CMOS process. It satisfies the DTV(ATSC) frequency band(54~806MHz). A scheme is proposed to cover the full band using only one VCO. The VCO has been designed to operate at 1.6~3.6GHz band such that the LO pulling effect is minimized, and reliable broadband characteristics have been achieved by reducing the variations of VCO gain and frequency step. The simulation results show that the designed VCO has gains of 59~94MHz(${\pm}$17.7MHz/V,${\pm}$23%) and frequency steps of 26~42.5MHz(${\pm}$8.25MHz/V,${\pm}$24%), and a very wide tuning range of 76.9%. The designed frequency synthesizer has a phase noise of -106dBc/Hz at 100kHz offset, and the lock time is less than $10{\mu}$sec. It consumes 20~23mA from a 1.8V supply, and the chip size including PADs is 2.0mm${\times}$1.8mm.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.9
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• pp.1985-1992
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• 2011

PE(Passive Entry) is an automotive technology which allows a driver to lock and unlock door of vehicle without using smart key buttons personally. PG(Pssive Go) is an automotive technology which offers the ability to start and stop the engine when there is a driver in vehicle with smart key. When these two functions are unified, we call it PEG(Passive Entry/Go). LF(Low Frequency) antenna driver which is one of core technologies in PEG is composed of a digital part which processes commands and an analog part which generates sine waveform. The digital part of antenna driver receives commands from MCU(or ECU), and processes requested commands by MCU, and stores antenna-related driver commands and data on an internal FIFO block. The digital part takes corresponding actions for commands read from FIFO and then transfers modulated LF data to analog part. The analog part generates sine waveform and transmits outside through antenna. The designed digital part for LF antenna driver can acomplish faster LF data transmission than that of conventional product. LF antenna driver can be applicable to the areas such as PEG for automotive and gate opening and closing of building.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.6
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• pp.860-866
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• 2016

An injection-locked ring phase-locked loop (ILRPLL) using a charge-stored complementary switch (CSCS) injection technique is described in this paper. The ILRPLL exhibits a wider lock range compared to other conventional ILRPLLs, owing to the improvement of the injection effect by the proposed CSCS. A frequency calibration loop and a device mismatch calibration loop force the frequency error to be zero to minimize jitter and reference spur. The prototype chip fabricated in 65-nm CMOS technology achieves a $285-fs_{rms}$ integrated jitter at GHz from the reference clock of 52 MHz while consuming 7.16 mW. The figure-of-merit of the ILRPLL is -242.4 dB.

• Journal of IKEEE
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• v.7 no.2 s.13
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• pp.236-244
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• 2003

In this paper, RF and IF circuits for mobile terminals which have usually been implemented using expensive BiCMOS processes are designed using CMOS circuits, and a Tx CMOS RF/IF single chip for PCS applications is designed. The designed circuit consists of an IF block including an IF PLL frequency synthesizer, an IF mixer, and a VGA and an RF block including a SSB RF mixer and a driver amplifier, and performs all transmit signal processing functions required between digital baseband and the power amplifier. The phase noise level of the designed IF PLL frequency synthesizer is -114dBc/Hz@100kHz and the lock time is less than $300{\mu}s$. It consumes 5.3mA from a 3V power supply. The conversion gain and OIP3 of the IF mixer block are 3.6dB and -11.3dBm. It consumes 5.3mA. The 3dB frequencies of the VGA are greater than 250MHz for all gain settings. The designed VGA consumes 10mA. The designed RF block exhibits a gain of 14.93dB and an OIP3 of 6.97dBm. The image and carrier suppressions are 35dBc and 31dBc, respectively. It consumes 63.4mA. The designed circuits are under fabrication using a $0.35{\mu}m$ CMOS process. The designed entire chip consumes 84mA from a 3V supply, and its area is $1.6㎜{\times}3.5㎜$.