• Title/Summary/Keyword: link-level simulation

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Transmit Power and Access Point Selection Algorithm: TA Link and AT Link (전송전력과 엑세스 포인트 선정 알고리즘: AT 링크와 TA 링크)

  • Oh, Changyoon
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.24 no.8
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    • pp.1022-1029
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    • 2020
  • We investigate the joint selection problem of the transmit power level and the best access point for multi-access points. We further reduce the transmit power by jointly optimizing the transmit power and the access point selection. Our aim is to minimize the total transmit power, while each terminal maintains minimum signal to interference ratio requirement. We observe that the optimum solution can be achieved through proposed iterative algorithm for both TA link and AT link. Simulation results show that proposed algorithm (joint optimization of transmit power level and access point) outperforms the algorithm which optimizes the transmit power only. We also observe that the duality between the TA link and AT link does not hold in multi-access points environment. Accordingly, the resulting power vectors and the access point vectors for TA link and AT link are different in general.

Design Guidelines for a Capacitive Wireless Power Transfer System with Input/Output Matching Transformers

  • Choi, Sung-Jin
    • Journal of Electrical Engineering and Technology
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    • v.11 no.6
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    • pp.1656-1663
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    • 2016
  • A capacitive wireless power transfer (C-WPT) system uses an electric field to transmit power through a physical isolation barrier which forms a pair of ac link capacitors between the metal plates. However, the physical dimension and low dielectric constant of the interface medium severely limit the effective link capacitance to a level comparable to the main switch output capacitance of the transmitting circuit, which thus narrows the soft-switching range in the light load condition. Moreover, by fundamental limit analysis, it can be proved that such a low link capacitance increases operating frequency and capacitor voltage stress in the full load condition. In order to handle these problems, this paper investigates optimal design of double matching transformer networks for C-WPT. Using mathematical analysis with fundamental harmonic approximation, a design guideline is presented to avoid unnecessarily high frequency operation, to suppress the voltage stress on the link capacitors, and to achieve wide ZVS range even with low link capacitance. Simulation and hardware implementation are performed on a 5-W prototype system equipped with a 256-pF link capacitance and a 200-pF switch output capacitance. Results show that the proposed scheme ensures zero-voltage-switching from full load to 10% load, and the switching frequency and the link capacitor voltage stress are kept below 250 kHz and 452 V, respectively, in the full load condition.

Fundamental Output Voltage Enhancement of Half-Bridge Voltage Source Inverter with Low DC-link Capacitance

  • Elserougi, Ahmed;Massoud, Ahmed;Ahmed, Shehab
    • Journal of Power Electronics
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    • v.18 no.1
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    • pp.116-128
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    • 2018
  • Conventionally, in order to reduce the ac components of the dc-link capacitors of the two-level Half-Bridge Voltage Source Inverter (HB-VSI), high dc-link capacitances are required. This necessitates the employment of short-lifetime and bulky electrolytic capacitors. In this paper, an analysis for the performance of low dc-link capacitances-based HB-VSI is presented to elucidate its ability to generate an enhanced fundamental output voltage magnitude without increasing the voltage rating of the involved switches. This feature is constrained by the load displacement factor. The introduced enhancement is due to the ac components of the capacitors' voltages. The presented approach can be employed for multi-phase systems through using multi single-phase HB-VSI(s). Mathematical analysis of the proposed approach is presented in this paper. To ensure a successful operation of the proposed approach, a closed loop current controller is examined. An expression for the critical dc-link capacitance, which is the lowest dc-link capacitance that can be employed for unipolar capacitors' voltages, is derived. Finally, simulation and experimental results are presented to validate the proposed claims.

A Multicoded-PPM Scheme for High Data Rate UWB Communication Systems

  • lung, Sung-Yoon;Park, Dong-Jo
    • Journal of Communications and Networks
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    • v.11 no.3
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    • pp.271-278
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    • 2009
  • A new modulation scheme called multicoded-pulse position modulation (MC-PPM) is proposed for an ultrawideband (UWB) impulse radio communication system. The multicoded signal is generated by using several orthogonal codes for transmitting data simultaneously. Then, each multi-level value of the multicoded signal is converted to pulse position which results in not only an improved data rate, but also a processing gain in reception, delivering the power-efficient benefit of PPM and guaranteeing the low pulse energy for UWB systems. We notice that the modulation of multi-level values of the multicoded signal to pulse position is more efficient in terms of achievable data rate than the modulation of transmitting data based on other PPM schemes within given bandwidth and pulse energy. Therefore, as a performance measure, we focus on the achievable data rate (link capacity) of the proposed scheme and analyze it theoretically. Through simulation, we compare the link capacity of the MC-PPM scheme and other PPM schemes, such as M -ary PPM and multiple PPM. With the fixed bandwidth and same pulse energy condition, the UWB system based on the proposed MC-PPM scheme shows good link capacity and an increased data rate as L increases, which is contrary to other PPM schemes.

Analysis of Neutral Point Current in T-Type Three-Level PWM Converter (T-type 3-레벨 PWM 컨버터의 중성점 전류 분석)

  • Lee, Kui-Jun
    • The Transactions of the Korean Institute of Power Electronics
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    • v.25 no.1
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    • pp.68-71
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    • 2020
  • As a T-type three-level PWM converter has several intrinsic advantages, it has been widely studied for many applications. However, it requires an additional voltage control loop for balancing each DC link voltage. Generally, satisfying this requirement involves the use of an offset voltage to provide a neutral point current without affecting other variables, such as the total DC link voltage and three-phase input current. In this study, the theoretical relationship between the offset voltage and the neutral point current is analyzed. The results can be beneficial for effective voltage balancing controller design. The effectiveness of the analytical modeling is verified by simulation and experimental results.

Estimating the DC Link Neutral Point Voltage to Improve Quality of Reactive Current for the 3-Level NPC topology (3-Level NPC 토폴로지의 무효전류 품질 향상을 위한 DC-Link 중성점 리플전압 예측 기법)

  • Lee, Yoon-min;Do, Won-Seok;Seo, Jungwon;Jung, Moon kwun;Kim, Hee jung;Kim, Young geun
    • Proceedings of the KIPE Conference
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    • 2019.07a
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    • pp.324-325
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    • 2019
  • 본 논문에서는 3-Level Neutral-Point-Clamped (NPC) 인버터의 중성점 리플 전압 예측 기법을 제안한다. 산업용 계통 연계형 인버터의 경우, 계통 규정을 만족하기 위하여 전압 강하와 같은 계통 사고 발생 시 계통에 협조할 수 있도록 무효전류 보상이 요구된다. NPC 인버터는 두 개의 커패시터가 직렬로 이루어진 구조로 무효전류 출력 시 상단과 하단의 커패시터 전압에 3차 중성점 리플 전류로 인해 중성점 리플 전압이 발생한다. 따라서 중성점 리플 전압을 고려하여 출력 전류에 보상하지 않으면 무효전류의 품질에 악영향을 끼칠 수 있다. 본 논문에서는 하나의 DC 전압센서를 통하여 중성점 전류를 예측하고, 중성점 리플 전압을 보상하는 알고리즘을 제안한다. Hardware In the Loop (HIL) Simulation을 통하여 본 논문에서 제안한 알고리즘의 타당성을 검증한다.

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Analysis of Capacitor Voltage and Boost Vector in Neutral-Point-Clamped and H-Bridge Converter (NPC와 H-Bridge 컨버더의 부스트 벡터와 커패시터 전압의 해석)

  • 김정균;김태진;강대욱;현동석
    • The Transactions of the Korean Institute of Power Electronics
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    • v.8 no.3
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    • pp.274-284
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    • 2003
  • Multi-level converter that is high-capacity electric power conversion system is used widely to electric motor drive system and FATCs(Flexible AC Transmission Systems). H-Bridge converter has been prevalently applied to shunt-type system because it can be easily expanded to the multi-level. In steady states, converter is normally operated in the range of 0.7∼0.8 of modulation Index. Even though zero vectors are not imposed to high modulation index, DC-Link voltage Is constant. It means that converter has another boost vector except for zero vectors among several vectors in 3-level converter. This paper has examined the principle of boost vector and investigated the difference between another boost vector and zero vectors in 3-level converter. In addition, this paper has analysed and compared the charging currents and the capacitor voltages of two topologies. The currents and voltages are related to reference voltage. Therefore, it proposed the calculation method for the voltage ripple and the charging current of each capacitor and compared various DC-Link voltage control methods through the simulation.

Hybrid simulation tests of high-strength steel composite K-eccentrically braced frames with spatial substructure

  • Li, Tengfei;Su, Mingzhou;Guo, Jiangran
    • Steel and Composite Structures
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    • v.38 no.4
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    • pp.381-397
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    • 2021
  • Based on the spatial substructure hybrid simulation test (SHST) method, the seismic performance of a high-strength steel composite K-eccentrically braced frame (K-HSS-EBF) structure system is studied. First, on the basis of the existing pseudostatic experiments, a numerical model corresponding to the experimental model was established using OpenSees, which mainly simulated the shear effect of the shear links. A three-story and five-span spatial K-HSS-EBF was taken as the prototype, and SHST was performed with a half-scale SHST model. According to the test results, the validity of the SHST model was verified, and the main seismic performance indexes of the experimental substructure under different seismic waves were studied. The results show that the hybrid simulation results are basically consistent with the numerical simulation results of the global structure. The deformation of each story is mainly concentrated in the web of the shear link owing to shear deformation. The maximum interstory drifts of the model structure during Strength Level Earthquake (SLE) and Maximum Considered Earthquake (MCE) meet the demands of interstory limitations in the Chinese seismic design code of buildings. In conclusion, the seismic response characteristics of the K-HSS-EBFs are successfully simulated using the spatial SHST, which shows that the K-HSS-EBFs have good seismic performance.

Provisioning QoS for WiFi-enabled Portable Devices in Home Networks

  • Park, Eun-Chan;Kwak, No-Jun;Lee, Suk-Kyu;Kim, Jong-Kook;Kim, Hwang-Nam
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.5 no.4
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    • pp.720-740
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    • 2011
  • Wi-Fi-enabled portable devices have recently been introduced into the consumer electronics market. These devices download or upload content, from or to a host machine, such as a personal computer, a laptop, a home gateway, or a media server. This paper investigates the fairness among multiple Wi-Fi-enabled portable devices in a home network when they are simultaneously communicated with the host machine. First, we present that, a simple IEEE 802.11-based home network suffers from unfairness, and the fairness is exaggerated by the wireless link errors. This unfairness is due to the asymmetric response of the TCP to data-packet loss and to acknowledgment-packet loss, and the wireless link errors that occur in the proximity of any node; the errors affect other wireless devices through the interaction at the interface queue of the home gateway. We propose a QoS-provisioning framework in order to achieve per-device fairness and service differentiation. For this purpose, we introduce the medium access price, which denotes an aggregate value of network-wide traffic load, per-device link usage, and per-device link error rate. We implemented the proposed framework in the ns-2 simulator, and carried out a simulation study to evaluate its performance with respect to fairness, service differentiation, loss and delay. The simulation results indicate that the proposed method enforces the per-device fairness, regardless of the number of devices present and regardless of the level of wireless link errors; furthermore it achieves high link utilization with only a small amount of frame losses.

Synchronization Method and Link Level Performance of DMB System A considering HPA Nonlineariry (HPA 비선형성을 고려한 DMB 시스템 A의 링크레벨 성능 및 동기화 기법)

  • Park SungHo;Cha Insuk;Chang KyungHi
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.30 no.6A
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    • pp.488-498
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    • 2005
  • The DAB(Digital Audio Broadcasting) service which is based on the Eureka-147 of Europe is developed to DMB(Digital Multimedia Broadcasting) service that is divided into Terrestrial DMB and Satellite DMB. The Satellite DMB is a new broadcasting service, which will service multi-channel multimedia broadcasting by the portable receiver or the vehicle receiver. In this paper, we consider that link level performance of satellite DMB system A which is based on the COFDM(Coded Orthogonal Division Multiplexing). It uses the OFDM method which is sensitive to nonlinearity, so we analyze the effect of the HPA(High Power Amplifier) nonlinearity. And then we define the appropriate back-off value by performing the link level simulation considering back-off effect. Also we consider the effect of frequency and time offset, and then confirm the overall link level performance by analyzing and verifying a suitable synchronization method for satellite DMB system A.