• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.11
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• pp.83-94
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• 2003

In this paper. a highly linear and low glitch CMOS current mode digital-to-analog converter (DAC) by self calibration bias circuit is proposed. The architecture of the DAC is based on a current steering 6＋4 segmented type and new switching scheme for the current cell matrix, which reduced non-linearity error and graded error. In order to achieve a high performance DAC . novel current cell with a low spurious deglitching circuit and a new inverse thermometer decoder are proposed. The prototype DAC was implemented in a 0.35${\mu}{\textrm}{m}$ n-well CMOS technology. Experimental result show that SFDR is 60 ㏈ when sampling frequency is 32MHz and DAC output frequency is 7.92MHz. The DAC dissipates 46 mW at a 3.3 Volt single power supply and occupies a chip area of 1350${\mu}{\textrm}{m}$ ${\times}$750${\mu}{\textrm}{m}$.

• Journal of KIISE
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• v.44 no.5
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• pp.537-544
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• 2017

As a special form of the signed-digit representation, the NAF(non-adjacent form) minimizes the hamming weight by reducing the average density of the non-zero bits from the binary representation of the positive integer k. Due to this advantage, the NAF is used in various fields; in particular, it is actively used in cryptology. The existing NAF-conversion algorithm, however, is problematic because the conversion speed decreases when the LSB(least significant bit) frequently becomes "1" during the binary positive integer conversion process. This paper suggests a method for the improvement of the NAF-conversion speed for which the problems that occur in the existing NAF-conversion process are solved. To verify the performance improvement of the algorithm, the CPU cycle for the various inputs were measured on the ATmega128, a low-performance 8-bit microprocessor. The results of this study show that, compared with the existing algorithm, the suggested algorithm not only improved the processing speed of the major patterns by 20% or more on average, but it also reduced the NAF-conversion time by 13% or more.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2001.10a
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• pp.617-620
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• 2001

This paper describes an efficient error-compensation technique for designing a low-error truncated Booth multiplier that receives two N-bit numbers and produces an N-bit product by eliminating the N least-significant bits. Applying the proposed method, a truncated Booth multiplier for area-efficient and low-power applications has been designed, and its performance (truncation error, area) was analyzed. Since the truncated Booth multiplier omits about half the partial product generators and adders, it has an area reduction by about 35%~40%, compared with non-truncated parallel multipliers. Error analysis shows that the proposed approach reduces the average truncation error by approximately 30%~40%, compared with conventional methods.

• ETRI Journal
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• v.35 no.4
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• pp.638-643
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• 2013

This paper presents a 5-bit digital step attenuator (DSA) using a commercial 0.18-${\mu}m$ silicon-on-insulator (SOI) process for the wideband phased array antenna. Both low insertion loss and low root mean square (RMS) phase error and amplitude error are achieved employing two attenuation topologies of the switched path attenuator and the switched T-type attenuator. The attenuation coverage of 31 dB with a least significant bit of 1 dB is achieved at DC to 20 GHz. The RMS phase error and amplitude error are less than $2.5^{\circ}$ and less than 0.5 dB, respectively. The measured insertion loss of the reference state is less than 5.5 dB at 10 GHz. The input return loss and output return loss are each less than 12 dB at DC to 20 GHz. The current consumption is nearly zero with a voltage supply of 1.8 V. The chip size is $0.93mm{\times}0.68mm$, including pads. To the best of the authors' knowledge, this is the first demonstration of a low phase error DC-to-20-GHz SOI DSA.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.13 no.6
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• pp.2908-2924
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• 2019

Multiple input multiple output orthogonal frequency division multiplexing (MIMO-OFDM) is widely applied in wireless communication by virtue of its excellent properties in data transmission rate and transmission accuracy. However, as a major drawback of MIMO-OFDM systems, the high peak-to-average power ratio (PAPR) complicates the design of the power amplifier at the receiver end. Some available PAPR reduction methods such as selective mapping (SLM) suffer from high computational complexity. In this paper, a low-complexity SLM method based on active constellation extension (ACE) and joint space-time selective mapping (AST-SLM) for reducing PAPR in Alamouti STBC MIMO-OFDM systems is proposed. In SLM scheme, two IFFT operations are required for obtaining each transmission sequence pair, and the selected phase vector is transmitted as side information(SI). However, in the proposed AST-SLM method, only a few IFFT operations are required for generating all the transmission sequence pairs. The complexity of AST-SLM is at least 86% less than SLM. In addition, the SI needed in AST-SLM is at least 92.1% less than SLM by using the presented blind detection scheme to estimate SI. We show, analytically and with simulations, that AST-SLM can achieve significant performance of PAPR reduction and close performance of bit error rate (BER) compared to SLM scheme.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.26 no.1
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• pp.5-15
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• 2016

Power analysis attacks are techniques to analyze power signals to find out the secrets when cryptographic algorithm is performed. One of the most famous countermeasure against power analysis attacks is masking methods. Masking types are largely classified into two types which are boolean masking and arithmetic masking. For the cryptographic algorithm to be used with boolean and arithmetic masking at the same time, the converting algorithm can switch between boolean and arithmetic masking. In this paper we propose an algorithm for switching from boolean to arithmetic masking using storage size at less cost than ones. The proposed algorithm is configured to convert using the look-up table without the least significant bit(LSB), because of equal the bit of boolean and arithmetic masking. This makes it possible to design a converting algorithm compared to the previous algorithm at a lower cost without sacrificing performance. In addition, by applying the technique at the LEA it showed up to 26 percent performance improvement over existing techniques.

• Korean Journal of Optics and Photonics
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• v.19 no.1
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• pp.60-67
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• 2008

An all-optical 4-bit Gray code to binary coded decimal (BCD) converter by means of commercially available numerical analysis tool (VPI) was demonstrated, for the first time to our knowledge. Circuit design approach was modified appropriately in order to fit the electrical method on an all-optical logic circuit based on a cross gain modulation (XGM) process so that signal degradation due to the non-ideal optical logic gates can be minimized. Without regenerations, Q-factor of around 4 was obtained for the most severely degraded output bit (least significant bit-LSB) with 2.5 Gbps clean input signals having 20 dB extinction ratio. While modifying the two-level simplification method and Karnaugh map method to design a Gray code to BCD converter, a general design concept was also founded (one-level simplification) in this research, not only for the Gray code to BCD converter but also for any general applications.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.14 no.4
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• pp.269-274
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• 2021

In secret communication, steganography is the sending and receiving of secret messages without being recognized by a third party. In the spatial domain method bitwise information is inserted into the virtual bit plane of the decomposed pixel values of the image. That is, the bitwise secret message is sequentially inserted into the least significant bit(LSB) of the image, which is a cover medium. In terms of application, the LSB is simple, but has a drawback that can be easily detected by a third party. If the upper bit plane is used to increase security, the image quality may deteriorate. In this paper, I present a method for concealing Hangul secret messages in image steganography based on the lo-th bit plane and the decomposition of modified pixel intensity values. After decomposing the Hangeul message to be hidden into choseong, jungseong and jongseong, then a shuffling process is applied to increase confidentiality and robustness. PSNR was used to confirm the efficiency of the proposed method. It was confirmed that the proposed technique has a smaller effect in terms of image quality than the method applying BCD and Fibonacci when inserting a secret message in the upper bit plane. When compared with the reference value, it was confirmed that the PSNR value of the proposed method was appropriate.

• Journal of Korea Society of Industrial Information Systems
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• v.20 no.3
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• pp.29-36
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• 2015

Steganography is the technique of hiding the existence of a secret message that is communicated hiddenly. Generally, the main objectives of this paper is to develop newer and more sophisticated steganographic techniques based on perceptual transparency, robustness and capacity of the hidden data. This paper analyzes the advantages and disadvantages of image steganography techniques and proposes an effective method. As a result, the images steganography technique based on good ELSB and DCT which applies the rearranged key is secure and effective.

• Journal of Korea Society of Digital Industry and Information Management
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• v.16 no.2
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• pp.1-9
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• 2020

Many cryptographic and error control coding algorithms rely on finite field GF(2m) arithmetic. Hardware implementation of these algorithms needs an efficient realization of finite field arithmetic operations. Finite field multiplication is complicated among the basic operations, and it is employed in field exponentiation and division operations. Various algorithms and architectures are proposed in the literature for hardware implementation of finite field multiplication to achieve a reduction in area and delay. In this paper, a low area and delay efficient semi-systolic multiplier over finite fields GF(2m) using the modified Montgomery modular multiplication (MMM) is presented. The least significant bit (LSB)-first multiplication and two-level parallel computing scheme are considered to improve the cell delay, latency, and area-time (AT) complexity. The proposed method has the features of regularity, modularity, and unidirectional data flow and offers a considerable improvement in AT complexity compared with related multipliers. The proposed multiplier can be used as a kernel circuit for exponentiation/division and multiplication.