• 한국인터넷방송통신학회논문지
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• 제24권1호
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• pp.37-42
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• 2024

본 논문은 NP-완전으로 최적 해를 구하는 다항시간 알고리즘이 알려져 있지 않은 절단 폭 최소화 문제에 대해 다항시간 알고리즘을 제안하였다. 주어진 그래프 G=(V,E),m=｜V｜, n=｜E｜ 에 대한 최소 절단 폭 CW_f(G)=max_𝜈∈_VCW_f(𝜈)를 찾기 위해 제안된 알고리즘은 첫 번째로, 최대차수 정점 𝜈_i를 기준으로 N_G[𝜈_i] 정점들을 𝜈_i를 통과하는 간선수가 최소가 되도록 양분하는 열 절단면을 찾고, 좌·우의 N_G[𝜈_i]들 간의 통과 간선수가 최소가 되는 행 절단면으로 분할하였다. 두 번째로, 각 부 그래프 내부의 정점들을 선형으로 연결하고, 부 그래프들 간 간선을 연결하여 하나의 선형 배열을 만들었다. 마지막으로, 정점을 이동시켜 최소 절단폭을 갖는 최적화 과정을 수행하였다. 다양한 그래프들을 대상으로 실험한 결과, 수행 복잡도가 O(n²)인 제안된 알고리즘을 모든 데이터들에 대해 최적 해를 찾을 수 있었다.

• 한국정보통신학회논문지
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• 제14권2호
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• pp.287-295
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• 2010

본 논문에서는 MPI(Message Passing Interface) 환경 하에서 채널배선 문제에 대한 분산 평균장 유전자 알고리즘(MGA, Mean field Genetic Algorithm)이라는 새로운 최적화 알고리즘을 제안한다. 분산 MGA는 평균장 어닐링(MFA, Mean Field Annealing)과 시뮬레이티드 어닐링 형태의 유전자 알고리즘(SGA, Simulated annealing-like Genetic Algorithm)을 결합한 경험적 알고리즘이다. 평균장 어닐링의 빠른 평형상태 도달과 유전자 알고리즘의 다양하고 강력한 연산자를 합성하여 최적화 문제를 효율적으로 해결하였다. 제안된 분산 MGA를 VLSI 설계에서 중요한 주제인 채널 배선문제에 적용하여 실험한 결과 기존의 GA를 단독으로 사용하였을 때보다 최적해에 빠르게 도달하였다. 또한 분산 알고리즘은 순차 알고리즘에서의 최적해 수렴 특성을 해치지 않으면서 문제의 크기에 대하여 선형적인 수행시간 단축을 나타냈다.

• 대한기계학회논문집A
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• 제25권12호
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• pp.1974-1980
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• 2001

The control algorithm of a new type self-bearing step motor is presented. The motor actuator is used for both motor and bearing functionality without any redundant coil windings or redundant electromagnets. The self$.$bearing step motor layout and its control method are described. A linearized farce-current-displacement relationship is derived. As the result of the unbalance response approach, the constant torque production is possible fur the supply current regulation algorithm. And even if the bearing functionality is added in the motor functionality, no additional current for bearing functionality is possible, and this leads to minimize the net power loss. Also, the unbalance response shows the independent bearing force and motor torque.

• 대한산업공학회지
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• 제27권3호
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• pp.281-288
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• 2001

We consider in this article a multi-objective part-machine grouping problem in which parts have alternative process plans and expected annual demand of each part is known. This problem is characterized as optimally determining part sets and corresponding machine cells such that total sum of distance (or dissimilarity) between parts and total sum of load differences between machines are simultaneously minimized. Two heuristic algorithms are proposed, and examples are given to compare the performance of the algorithms.

• 한국경영과학회지
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• 제23권1호
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• pp.17-28
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• 1998

This study suggests a procedure for designing cellular manufacturing systems (CMS) which are combined with automated guided vehicles (AGVs) using a tandem configuration. So far most of the previous studies have dealt with conventional design problems not considering the layout and the characteristics of transporters used in CMS. A mathematical model is developed using the service time to perform material transfers as a suitable meassure. The service capacity of AGVs and space limitations are also reflected in this model. As the model can be shown strongly NP-hard, a heuristic algorithm is presented, in which each cell is temporarily formed using both the set covering model and similarity coefficients, and then locations of the cells are determined by means of tabu search and finally machine perturbations are carried out. An example problem is solved to demonstrate the algorithm developed.

• 한국항해항만학회지
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• 제32권9호
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• pp.737-742
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• 2008

In this paper, we deal with an allocation model of vertical type container yard for minimizing the total ATC (Automated Transfer Crane) working time and the equivalence of ATC working load in each block on automated container terminal. Firstly, a layout of automated container terminal yard is shown The characteristic of equipment which work in the terminal and its basic assumption are given Next, an allocation model which concerns with minimizing the total working time and the equivalence of working load is proposed for effectiveness of ATC working in automated container terminal. Also, a weight values on critical function are suggested to adjust the critical values by evaluating the obtained allocation plan. For ATC allocation algorithm, we suggest a simple repeat algorithm for on-line terminal operation.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권5호
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• pp.582-594
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• 2016

Various test data compression techniques have been developed to reduce the test costs of system-on-a-chips. In this paper, a scan chain reordering algorithm for code-based test data compression techniques is proposed. Scan cells within an acceptable relocation distance are ranked to reduce the number of conflicts in all test patterns and rearranged by a positioning algorithm to minimize the routing overhead. The proposed method is demonstrated on ISCAS '89 benchmark circuits with their physical layout by using a 180 nm CMOS process library. Significant improvements are observed in compression ratio and test power consumption with minor routing overhead.

• 대한전자공학회논문지
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• 제25권1호
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• pp.101-107
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• 1988

This paper proposes a circuit extractor which extracts a netlist from the CIF input file cntaining the layout mask artwork informations. The circuit extractor extracts transistors and their interconnections, and calculates circuit parameter such as parasitic resistance and parasitic capacitance from the mask informations. When calculating the parasitic resistance, we consider the current flow path to reduce the errors caused by the resistance approximation. Similarly, we consider the coupling capacitance which has an effect on the circuit characteristics, when the parasitic capacitances are calculated. Therefore, using these parameter values as an input to circuit simulation, the circuit characteristics such as delay time can be estimated accurately. The presented circuit extraction algorithm uses a multiple storage quad tree as a data sturucture for storing and searching the 2-dimensional geometric data of mask artwork. Also, the proposed algorithm is technologically independent to work across a wide range of MOS technologies without any change in the algorihm.

• Computational Structural Engineering : An International Journal
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• 제1권1호
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• pp.21-29
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• 2001

The general topology optimization can be considered as optimal material distribution. Such an approach can be unstable, unless composite materials are introduced. In this research, a nodal volume fraction method is used to obtain the optimum topology of continuum structures. This method is conducted from a composite material model composed of isotropic matter and spherical void. Because the appearance of the chessboard patterns makes the interpretation of the optimal material layout very difficult, this method contains a chessboard prevention strategy. In this research, several topology optimization problems are presented to demonstrate the validity of the present method and the recursive quadratic programming algorithm is used to solve the topology optimization problems.

• 전자공학회논문지A
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• 제31A권4호
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• pp.127-135
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• 1994

In this paper we propose an EWLD(Enhanced Weighted Levenshtein Distance) algorithm to organize code-string pattern matching linear array processor based on the mappting to an one-dimensional array from a two-dimensional matching matrix, and design a processing element(PE) of the processor, N PEs are required instead of NS02T in the processor because of the mapping. Data input and output between PEs and all internal operations of each PE are performed in bit-serial fashion. The bit-serial operation consists of the computing of word distance (WD) by comparison and the selection of optimal code transformation path, and takes 22 clocks as a cycle. The layout of a PE is designed based on the double metal $1.5\mu$m CMOS rule. About 1,800 transistors consistute a processing element and 2 PEs are integrated on a 3mm$\times$3mm sized chip.