• Journal of the Korean Institute of Telematics and Electronics
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• v.23 no.4
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• pp.550-556
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• 1986

This paper proposes a two-layer channel routing algorithm using the division of signal nets in LSI/VLSI layout design. To solve the vertical constraint problem, the doglegging method is used. Although signal net division and the dogleg are used, the routing is accomplished within local channel density and the increase in vias is repressed by assining the vertical segments to the metal layer and the horizontal segments to the poly layer. The algorithm was implemented on a VAX 11/780 computer. The effectiveness of the proposed algorithm is proved by appling this algorithm to Deutch's difficult example.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.24 no.2
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• pp.186-191
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• 2020

In this paper, we proposed an optimization technique for efficiently placing vehicles on decks in a vehicle-carrying ship to efficiently handle loading and unloading. For this purpose, we utilized the transformation method of the XML data representing the ship's spatial information, merging and branching algorithm and genetic algorithm, and implemented the function to visualize the optimized vehicle placement results. The techniques of selection, crossover, mutation, and elite preservation, which are used in the conventional genetic algorithms, are used. In particular, the vehicle placement optimization method is proposed by merging and branching the ship space for the vehicle loading. The experimental results show that the proposed merging and branching method is effective for the optimization process that is difficult to optimize with the existing genetic algorithm alone. In addition, visualization results show vehicle layout results in the form of drawings so that experts can easily determine the efficiency of the layout results.

• Journal of the Korean Institute of Telematics and Electronics
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• v.25 no.5
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• pp.572-579
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• 1988

In this paper, a system of automatic placement and routing for gate array layout design is proposed. In the placement stage, the circuit is partitioned and using the concept of min-cut slicing, and each partitioned module is placed, so that the routing density over the entire chip be uniformized and the total wiring length be minimized. In the global routing stage, the concept of the probabilistic routing density is introduced to unify the wiring congestions in each channel. In the detailed routing stage, the multi-terminal nets are partitioned into the two-terminal nets. The ordered channel graph is proposed which implies the vertical and the horizontal constranint graphs simultaneously. And using the ordered channel graph, the proposed routing algorithm assigns the signal nets to the tracks. Also the proposed placement and routing algorithms are implimented on IBM/PC-AT to construct PC-level gate array layout system.

• Journal of the Korean Operations Research and Management Science Society
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• v.26 no.1
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• pp.71-85
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• 2001

This paper considers a cost model for a U-shaped manufacturing cell formation which incorporates a required number of machines and various material flows together under multi-part multi-cell environment. The model is required to satisfy both the specified operation sequence of each part and the total part demand volume, which are considered to derive material handling cost in U-shaped flow line cells. In the model several cost-incurring factors including set-up for batch change-over, processing time for operations of each part, and machine failures are also considered in association with processing load and capacity of each cell. Moreover, a heuristic for a good machine layout in each cell is newly proposed based on the material handling cost of each alternative sequence layout. These all are put together to present an efficient heuristic for the U-shaped independent-cell formation problem, numerical problems are solved to illustrate the algorithm.

• Journal of the Korean Operations Research and Management Science Society
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• v.14 no.1
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• pp.16-26
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• 1989

The terminal layout problem is fundamental in may centralized computer networks, which is generated formulated as the capaciated minimum spanning tree problem (CMSTP). We present an implementation of the dual-based procedure to solve the CMSTP. Dual ascent procedure generates a good feasible solutions to the dual of the linear programming relaxation of CMSTP. A feasible primal solution to CMSTP can then be constructed based on this dual solution. This procedure can be used either as a stand-alone heuristic or, else, it can be incorporated into a branch and bound algorithm. A numerical result is given with quite favorable results.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.6
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• pp.115-123
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• 1989

This paper describes a new method of mask compaction to formulate a mixed integer linear programming problem from a user defined stick diagram. By solving this mixed integer program, a compacted and design rule violation free layout is obtained. Also, a new efficient algorithm is given which solves the longest problem in the constraint graph.

• Journal of the Korean Institute of Telematics and Electronics
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• v.24 no.6
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• pp.1049-1055
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• 1987

This paper describes a near-optimal standard cell layout strategy which consists of three consecutives steps` partition, placement, and routing. In the partition step, a given network is torn apart into many subnetworks such that each subnetworks contains as many cells as possible with minimum interocnnections between subnetwork. In the placement step, the conventional string placement algorithm was modified. Also, bonding pads were placed such that their connections to the related cells are shortest. As a result for the tested example, the placement time was saved by 60% and the total routing lengths were saved by more than 20% and substantial improvements in the number of feed-through cell and the track density were obtained. The layout program is coded in PASCAL and implemented on a VAX 11-750/UNIX computer.

• Proceedings of the Computational Structural Engineering Institute Conference
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• 2006.04a
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• pp.805-812
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• 2006

An optimization formulation is proposed to minimize sound pressures in a two-dimensional cavity by controlling the attachment area of unconstrained damping materials. For the analysis of structural-acoustic systems, a hybrid approach that uses finite elements for structures and boundary elements for cavity is adopted. Four-parameter fractional derivative model is used to accurately represent dynamic characteristics oJ the viscoelastic materials with frequency and temperature. Optimal layouts of the unconstrained damping layer on structural wall of cavity are identified according to temperatures and the amount of damping material by using a numerical search algorithm.

• Journal of the Korean Society for Precision Engineering
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• v.18 no.10
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• pp.93-100
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• 2001

The analysis and control of a new type unsymmetrical slotted self-bearing step motor for small angle control is presented. The motor actuator is used for both motor and bearing functionality without any additional coil windings or electromagnets for bearing functionality. A circular-arc, straight-line permeance model for the fringing effect is presented. An unsymmetrical slotted self-bearing step motor layout and control algorithm are described. A new control current generation method using the electromagnets layout geometry, which needs no additional current for bearing functionality, is proposed. As the result of this analysis the fringing effect largely influences on the system characteristics. especially in torque. Even if the bearing functionality is added into the motor functionality, it is shown that the magnitude of torque is not changed.

• Proceedings of the IEEK Conference
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• 2002.07c
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• pp.1539-1542
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• 2002

In layout of LSI and PWB, block pack- ing problem is very important in order to reduce chip area. Sequence-pair is typical one of conventional pack- ing method and can search nearly-optimal solution by using Simulated Annealing(SA). SA takes huge computation time due to evaluating of various packing results. Therefore, Sequence-pair is not effective enough for fast layout evaluation including estimation of wire length and rotation of every blocks. This paper proposes an efficient block packing method to minimize wire length and chip area. Our method searches an optimal packing efficient- ly by using a cluster growth algorithm with changing the most valuable packing score on packing process.