• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2003년도 추계학술대회 논문집 Vol.16
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• pp.163-166
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• 2003

The electrothermal simulation of high voltage LIGBT(Lateral Insulated Gate Bipolar Transistor) in thin Silicon on insulator (SOI) and Silicon on sapphire (SOS) for thermal conductivity and sink is performed by means of MEDICI. The finite element simulations demonstrate that the thermal conductivity of the buried oxide is an important parameter for the modeling of the thermal behavior of silicon-on-insulator (SOI) devices. In this paper, using for SOI LIGBT, we simulated electrothermal for device that insulator layer with $SiO_2\;and\;Al_2O_3$ at before and after latch up to measured the thermal conductivity and temperature distribution of whole device and verified that SOI LIGBT with $Al_2O_3$ insulator had good thermal conductivity and reliability

• Journal of Power Electronics
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• 제9권3호
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• pp.464-471
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• 2009

This paper introduces a new Motion-$SPM^{TM}$ (Smart Power Modules) module in Single In-line Package (SIP), which is a fully optimized intelligent integrated IGBT inverter module for up to 1kW low power motor drive applications. This module offers a sophisticated, integrated solution and tremendous design flexibility. It also takes advantage of pliability for the arrangement of heat-sink due to two types of lead forms. It comes to be realized by employing non-punch-through (NPT) IGBT with a fast recovery diode and highly integrated building block, which features built-in HVICs and a gate driver that offers more simplicity and compactness leading to reduced costs and high reliability of the entire system. This module also provides technical advantages such as the optimized cost effective thermal performances through IMS (Insulated Metal Substrate), the high latch immunity. This paper provides an overall description of the Motion-$SPM^{TM}$ in SIP as well as actual application issues such as electrical characteristics, thermal performance, circuit configurations and power ratings.

• 전자공학회논문지C
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• 제36C권11호
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• pp.10-17
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• 1999

본 논문에서는 MOS 트랜지스터로만 이루어진 CMOS IADC(Current-mode Analog-to-Digital Converter)를 설계하였다. 각 단은 CSH(Current Sample-and-Hold)와 CCMP(Current Comparator)로 구성된 1.5-비트 비트 셀로 구성되었다. 비트 셀 전단은 CFT(Clock Feedthrough)가 제거된 9-비트 해상도의 차동 CSH를 배치하였고, 각 단 비트 셀의 ADSC(Analog-to-Digital Subconverter)는 2개의 래치 CCMP로 구성되었다. 제안된 IADC를 현대 0.65 ㎛ CMOS 파라미터로 ACAD 시뮬레이션 한 결과, 20 Ms/s에서 100 ㎑의 입력 신호에 대한 SINAD(Signal to Noise-Plus-Distortion)은 47 ㏈ SNR (Signal-to-Noise)는 50 ㏈(8-bit)을 얻었고 35.7 ㎽ 소비전력 특성을 나타냈다.

• IEIE Transactions on Smart Processing and Computing
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• 제4권4호
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• pp.291-296
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• 2015

This paper describes the design of a high-speed comparator for high-speed automatic test equipment (ATE). The normal comparator block, which compares the detected signal from the device under test (DUT) to the reference signal from an internal digital-to-analog converter (DAC), is composed of a rail-to-rail first pre-amplifier, a hysteresis amplifier, and a third pre-amplifier and latch for high-speed operation. The proposed continuous comparator handles high-frequency signals up to 800MHz and a wide range of input signals (0~5V). Also, to compare the differences of both common signals and differential signals between two DUTs, the proposed differential mode comparator exploits one differential difference amplifier (DDA) as a pre-amplifier in the comparator, while a conventional differential comparator uses three op-amps as a pre-amplifier. The chip was implemented with $0.18{\mu}m$ Bipolar CMOS DEMOS (BCDMOS) technology, can compare signal differences of 5mV, and operates in a frequency range up to 800MHz. The chip area is $0.514mm^2$.

• 대한전자공학회논문지SD
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• 제46권12호
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• pp.105-112
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• 2009

본 논문에서는 $0.35{\mu}m$ Bipolar-CMOS-DMOS(BCD)공정으로 설계한 스마트 파워 IC 내의 가드링 코너 영역에서 발생하는 비정상적인 정전기 불량을 관측하고 이를 분석하였다. 칩내에서 래치업(Latch-up)방지를 위한 고전압 소자의 가드링에 연결되어 있는 Vcc단과 Vss 사이에 존재하는 기생 다이오드에서 발생한 과도한 전류 과밀 현상으로 정전기 내성 평가에서 Machine Model(MM)에서는 200V를 만족하지 못하는 불량이 발생하였다. Optical Beam Induced Resistance Charge(OBIRCH)와 Scanning Electronic Microscope(SEM)을 사용하여 불량이 발생한 지점을 확인하였고, 3D T-CAD 시뮬레이션으로 원인을 검증하였다. 시뮬레이션 결과를 통해 Local Oxidation(LOCOS)형태의 Isolation구조에서 과도한 정전기 전류가 흘렀을 때 코너영역의 형태에 따라 문제가 발생하는 것을 검증하였다. 이를 통해 정전기 내성이 개선된 가드링 코너 디자인 방법을 제안하였고 제품에 적용한 결과, MM 정전기 내성 평가에서 200V이상의 결과를 얻었다. 통계적으로 Test chip을 분석한 결과 기존의 결과 대비 20%이상 정전기 내성이 향상된 것을 확인 할 수 있었다. 이 결과를 바탕으로 BCD공정을 사용하는 칩 설계 시, 가드링 구조의 정전기 취약 지점을 Design Rule Check(DRC) 툴을 사용하여 자동으로 찾을 수 있는 설계 방법도 제안하였다. 본 연구에서 제안된 자동 검증방법을 사용하여, 동종 제품에 적용한 결과 24개의 에러를 검출하였으며, 수정 완료 제품은 동일한 정전기 불량은 발생하지 않았고 일반적인 정전기 내성 요구수준인 HBM 2000V / MM 200V를 만족하는 결과를 얻었다.

• Journal of Astronomy and Space Sciences
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• 제29권3호
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• pp.315-320
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• 2012

We developed a mass-memory chip by staking 1 Gbit double data rate 2 (DDR2) synchronous dynamic random access memory (SDRAM) memory core up to 4 Gbit storage for future satellite missions which require large storage for data collected during the mission execution. To investigate the resistance of the chip to the space radiation environment, we have performed heavy-ion-driven single event experiments using Heavy Ion Medical Accelerator in Chiba medium energy beam line. The radiation characteristics are presented for the DDR2 SDRAM (K4T1G164QE) fabricated in 56 nm technology. The statistical analyses and comparisons of the characteristics of chips fabricated with previous technologies are presented. The cross-section values for various single event categories were derived up to ~80 $MeVcm^2/mg$. Our comparison of the DDR2 SDRAM, which was fabricated in 56 nm technology node, with previous technologies, implies that the increased degree of integration causes the memory chip to become vulnerable to single-event functional interrupt, but resistant to single-event latch-up.

• 전기학회논문지
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• 제62권5호
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• pp.639-642
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• 2013

In this paper, proposed NED(nuclear event detectors) for detection of a transient radiation. Nuclear event detector was blocked of power temporary for defence of critical damage at a electric device when a induced transient radiation. Conventional NED consist of BJT, resistors and capacitors. The NED supply voltage of 5V and MCM(Multi Chip Module) structures. The proposed NED were designed for low supply voltage using 0.18um CMOS process. The response time of proposed NED was 34.8ns. In addition, pulse radiation experiments using a electron beam accelerator, the output signal has occurred.

• 한국위성정보통신학회논문지
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• 제11권4호
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• pp.21-26
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• 2016

PPS 소자가 삽입된 N형 실리콘 제어 정류기(NSCR_PPS) 소자에서 채널차단영역의 이온주입 변화가 정전기 보호 성능에 미치는 영향을 연구하였다. 종래의 NSCR 표준소자는 on 저항, 스냅백 홀딩 전압 및 열적 브레이크다운 전압이 너무 낮아 마이크로칩의 정전기보호소자로 적용이 어려웠다. 그러나 본 연구에서 제안하는 채널 차단 영역의 이온주입 조건을 변화시켜 각각 변형설계된 소자에서는 채널 차단 이온주입이 정전기 보호성능의 향상에 영향을 주는 중요한 파라미터였으며, CPS_PDr+HNF 구조의 변형소자는 정전기보호소자의 설계창을 만족시키는 향상된 정전기보호성능을 나타내어 고전압 동작용 마이크로 칩의 정전기보호 소자로 적용 가능함을 확인하였다.

• ETRI Journal
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• 제38권2호
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• pp.272-279
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• 2016

In this paper, a new structure for an advanced high holding voltage silicon controlled rectifier (AHHVSCR) is proposed. The proposed new structure specifically for an AHHVSCR-based electrostatic discharge (ESD) protection circuit can protect integrated circuits from ESD stress. The new structure involves the insertion of a PMOS into an AHHVSCR so as to prevent a state of latch-up from occurring due to a low holding voltage. We use a TACD simulation to conduct a comparative analysis of three types of circuit - (i) an AHHVSCR-based ESD protection circuit having the proposed new structure (that is, a PMOS inserted into the AHHVSCR), (ii) a standard AHHVSCR-based ESD protection circuit, and (iii) a standard HHVSCR-based ESD protection circuit. A circuit having the proposed new structure is fabricated using $0.18{\mu}m$ Bipolar-CMOS-DMOS technology. The fabricated circuit is also evaluated using Transmission-Line Pulse measurements to confirm its electrical characteristics, and human-body model and machine model tests are used to confirm its robustness. The fabricated circuit has a holding voltage of 18.78 V and a second breakdown current of more than 8 A.

• JSTS:Journal of Semiconductor Technology and Science
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• 제15권6호
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• pp.601-607
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• 2015

A set of novel silicon controlled rectifier (SCR) devices' characteristics have been analyzed and verified under the electrostatic discharge (ESD) stress. A ring-shaped diffusion was added to their anode or cathode in order to improve the holding voltage (Vh) of SCR structure by creating new current discharging path and decreasing the emitter injection efficiency (${\gamma}$) of parasitic Bipolar Junction Transistor (BJT). ESD current density distribution imitated by 2-dimensional (2D) TCAD simulation demonstrated that an additional current path exists in the proposed SCR. All the related devices were investigated and characterized based on transmission line pulse (TLP) test system in a standard $0.5-{\mu}m$ 24 V CDMOS process. The proposed SCR devices with ring-shaped anode (RASCR) and ring-shaped cathode (RCSCR) own higher Vh than that of Simple SCR (S_SCR). Especially, the Vh of RCSCR has been raised above 33 V. What's more, their holding current is kept over 800 mA, which makes it possible to design power clamp with SCR structure for on chip ESD protection and keep the protected chip away from latch-up risk.