• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.1
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• pp.151-157
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• 2013

In this paper, a comparative analysis of PBTI induced device degradation in nanowire n-channel junctionless and inversion mode Multiple-Gate MOSFET(MuGFETs) has been performed. It has been observed that the threshold voltage is increased after PBTI stress and the threshold voltage variation of junctionless device is less significant than that of inversion mode device. However the degradation rate of junctionless device is less significant than that of inversion mode device. The activation energy of the device degradation is larger in inversion mode device than junctionless device. In order to analyze the more significant PBTI induced device degradation in inversion mode device than junctionless device, 3-dimensional device simulation has been performed. The electron concentration in inversion mode device is equal to the one in junctionless device but the electric field in inversion mode device is larger than junctionless device.

• Journal of IKEEE
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• v.19 no.4
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• pp.514-519
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• 2015

We propose the multiple gate structure of double gate junctionless metal oxide silicon field oxide transistor (JL MOSFET) for device optimization. Since different workfunction within multiple metal gates, electric potential nearby source and drain region is modulated in accordance with metal gate length. On current, off current and threshold voltage are influenced with gate structure and make possible to meet some device specification. Through the device simulation work, performance optimization of double gate JL MOSFETs are introduced and investigated.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.4
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• pp.789-794
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• 2017

Subthreshold current model is presented using analytical potential distribution of junctionless cylindrical surrounding-gate (CSG) MOSFET and threshold voltage shift is analyzed by this model. Junctionless CSG MOSFET is significantly outstanding for controllability of gate to carrier flow due to channel surrounded by gate. Poisson's equation is solved using parabolic potential distribution, and subthreshold current model is suggested by center potential distribution derived. Threshold voltage is defined as gate voltage corresponding to subthreshold current of $0.1{\mu}A$, and compared with result of two dimensional simulation. Since results between this model and 2D simulation are good agreement, threshold voltage shift is investigated for channel dimension and doping concentration of junctionless CSG MOSFET. As a result, threshold voltage shift increases for large channel radius and oxide thickness. It is resultingly shown that threshold voltage increases for the large difference of doping concentrations between source/drain and channel.

• Journal of IKEEE
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• v.22 no.1
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• pp.74-79
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• 2018

We analyzed the relationship between center potential and subthreshold swing (SS) of Junctionless Cylindrical Surrounding Gate (JLCSG) and Junctionless Double Gate (JLDG) MOSFET. The SS was obtained using the analytical potential distribution and the center potential, and SSs were compared and investigated according to the change of channel dimension. As a result, we observed that the change in central potential distribution directly affects the SS. As the channel thickness and oxide thickness increased, the SS increased more sensitively in JLDG. Therefore, it was found that JLCSG structure is more effective to reduce the short channel effect of the nano MOSFET.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.31 no.5
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• pp.278-282
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• 2018

We propose a SPICE model of drain-induced barrier lowering (DIBL) for a junctionless cylindrical surrounding gate (JLCSG) MOSFETs. To this end, the potential distribution in the channel is obtained via the Poisson equation, and the threshold voltage model is presented for the JLCSG MOSFET. In a JLCSG nano-structured MOSFET, a channel radius affects the carrier transfer as well as the channel length and oxide thickness; therefore, DIBL should be expressed as a function of channel length, channel radius, and oxide thickness. Consequently, it can be seen that DIBLs are proportional to the power of -3 for the channel length, 2 for the channel radius, 1 for the thickness of the oxide film, and the constant of proportionality is 18.5 when the SPICE parameter, the static feedback coefficient ${\eta}$, is between 0.2 and 1.0. In particular, as the channel radius and the oxide film thickness increase, the value of ${\eta}$ remains nearly constant.

• Proceeding of EDISON Challenge
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• 2014.03a
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• pp.420-424
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• 2014

본 논문에서는 접합을 가지지 않는 Junctionless transistor (JLT)의 두께에 따른 특성 차이 및 기존의 MOSFET과의 특성 비교를 EDISON 시뮬레이터를 통해 확인을 하였다. JLT의 두께가 얇아짐에 따라 On/off 비율 측면에서 소자의 특성이 향상됨을 확인 하였으며, 기존 Inversion mode의 MOSFET과 비교하여 단 채널 효과 측면에서도 향상된 특성을 확인 할 수 있었다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.32 no.2
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• pp.104-109
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• 2019

An analytical threshold voltage model is proposed to analyze the threshold voltage roll-off and drain-induced barrier lowering (DIBL) for a junction-based double-gate (JBDG) MOSFET and a junction-less double-gate (JLDG) MOSFET. We used the series-type potential distribution function derived from the Poisson equation, and observed that it is sufficient to use n=1 due to the drastic decrease in eigenvalues when increasing the n of the series-type potential function. The threshold voltage derived from this threshold voltage model was in good agreement with the result of TCAD simulation. The threshold voltage roll-off of the JBDG MOSFET was about 57% better than that of the JLDG MOSFET for a channel length of 25 nm, channel thickness of 10 nm, and oxide thickness of 2 nm. The DIBL of the JBDG MOSFET was about 12% better than that of the JLDG MOSFET, at a gate metal work-function of 5 eV. It was also found that decreasing the work-function of the gate metal significantly reduces the DIBL.

• Journal of Electrical Engineering and Technology
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• v.8 no.6
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• pp.1497-1502
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• 2013

Recently, the junctionless (JL) transistors realized by a single-type doping process have attracted attention instead of the conventional metal-oxide-semiconductor field-effect transistors (MOSFET). The JL transistor can overcome MOSFET's problems such as the thermal budget and short-channel effect. Thus, the JL transistor is considered as great alternative device for a next generation low standby power silicon system. In this paper, the JL FinFET was simulated with a three dimensional (3D) technology computer-aided design (TCAD) simulator and optimized for DC characteristics according to device dimension and doping concentration. The design variables were the fin width ($W_{fin}$), fin height ($H_{fin}$), and doping concentration ($D_{ch}$). After the optimization of DC characteristics, RF characteristics of JL FinFET were also extracted.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.31 no.3
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• pp.146-151
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• 2018

In this study, we compared the threshold-voltage extraction methods of accumulation-type JLDG (junctionless double-gate) MOSFETs (metal-oxide semiconductor field-effect transistors). Threshold voltage is the most basic element of transistor design; therefore, accurate threshold-voltage extraction is the most important factor in integrated-circuit design. For this purpose, analytical potential distributions were obtained and diffusion-drift current equations for these potential distributions were used. There are the ${\phi}_{min}$ method, based on the physical concept; the linear extrapolation method; and the second and third derivative method from the $I_d-V_g$ relation. We observed that the threshold-voltages extracted using the maximum value of TD (third derivatives) and the ${\phi}_{min}$ method were the most reasonable in JLDG MOSFETs. In the case of 20 nm channel length or more, similar results were obtained for other methods, except for the linear extrapolation method. However, when the channel length is below 20 nm, only the ${\phi}_{min}$ method and the TD method reflected the short-channel effect.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.34 no.2
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• pp.142-147
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• 2021

We present a subthreshold swing model for a symmetric junctionless double gate MOSFET. The scale length λ1 required to obtain the potential distribution using the Poisson's equation is a criterion for analyzing the short channel effect by an analytical model. In general, if the channel length Lg satisfies Lg > 1.5λ1, it is known that the analytical model can be sufficiently used to analyze short channel effects. The scale length varies depending on the channel and oxide thickness as well as the dielectric constant of the channel and the oxide film. In this paper, we obtain the scale length for a constant permittivity (silicon and silicon dioxide), and derive the relationship between the scale length and the channel length satisfying the error range within 5%, compared with a numerical method. As a result, when the thickness of the oxide film is reduced to 1 nm, even in the case of Lg < λ1, the analytical subthreshold swing model proposed in this paper is observed to satisfy the error range of 5%. However, if the oxide thickness is increased to 3 nm and the channel thickness decreased to 6 nm, the analytical model can be used only for the channel length of Lg > 1.8λ1.