• 한국콘텐츠학회:학술대회논문집
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• 한국콘텐츠학회 2003년도 춘계종합학술대회논문집
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• pp.403-405
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• 2003

학부생들이 쉽게 사용할 수 있는 기법인 반복 그린함수 방법(IGFM)을 이용하여 복잡한 전자파 도파관 구조를 이론적으로 해석한다. IGFM은 그린함수와 반복법을 이용한다. IGFM의 간단한 공식화를 위해 단순한 수학 방정식만을 사용한 물리적인 메커니즘을 이용한다. 전형적인 전자파 도파관 구조인 평행판 E평면 T접합에 대한 산란 특성을 IGFM 관점에서 이론적으로 공식화한다. 수치해석 결과를 주파수에 대한 반사와 투과 전력 관점에서 보인다. 우세모드 해를 유도하고 그 결과를 고차모드에 의한 해와 비교한다.

• 한국콘텐츠학회논문지
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• 제7권2호
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• pp.125-131
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• 2007

학부생들이 쉽게 사용할 수 있는 기법인 반복 그린 함수 방법(IGFM)을 이용하여 복잡한 전자파 도파관스텁 구조를 이론적으로 엄밀하게 해석한다. lGFM은 그린 함수 접근법과 영역 반복법을 이용한다. IGFM의 간단한 공식화를 위해 단순한 수학 방정식만을 사용한 물리적인 반복 메커니즘을 이용한다. 전형적인 전자파 도파관 구조인 평행판 E평면 T접합 스텁에 대한 산란 특성을 IGFM 관점에서 이론적으로 공식화한다. 수치해석 결과를 주파수에 대한 반사와 투과 전력 관점에서 보인다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 하계종합학술대회논문집
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• pp.405-408
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• 1998

Due to the large conduction band discontinuity between emitter base, OmGaAs HBT has an advantge to enable the hot electrons to inject into the base. In this paper, InAlGaAs/InGaAs HBT with the various emitter junction gradings and the modified collectors are simulated and analyzed by HMC(hybrid monte carlo) simulator in order to find a optimal structure for the shortest transit time. A minium base transit time (.tau.$_{b}$ ) of 0.21 ps was obtained for HBT with the grading layer, which is parabolically graded from x=1.0 to x=0.5. The minimum collector transit time (.tau.$_{c}$ ) of 0.31ps was found when the collector was modified by inserting p$^{[-10]}$ and p$^{+}$ layers. Thus HBT in combination with the emitter grading and the modified collector layer showed the cut-off frequency (f$_{T}$) of 183GHz.z.z.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2002년도 하계학술대회 논문집
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• pp.78-81
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• 2002

This paper describes on the design structure and development temperature stable strip-line junction isolator operating in above resonance mode. Temperature characteristics of isolator depend on magnet, YIG(Yttium Iron Garnet) ferrite, and conductor etc. These require temperature stability and possible methods of compensation for the temperature dependent effects. In this paper, the analysis and measurement of the temperature characteristics were carried out for the material isolator prototype. The bandwidth of isolator was expended and the center frequency shift was reduced in temperature range of -20∼8O$^{\circ}C$.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2001년도 하계학술대회 논문집 C
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• pp.1442-1444
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• 2001

A new low-temperature poly-Si TFT employing a counter-doped lateral body terminal is proposed and fabricated, in order to enhance the stability of poly-Si TFT driving circuits. The LBT structure effectively suppresses the kink effect by collecting the counter-polarity carriers and suppresses the hot carrier effect by reducing the peak lateral field at the drain junction. The proposed device is immune to dynamic stress, so that it is suitable for low voltage and high speed driving circuits of AMLCD.

• 전자공학회논문지A
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• 제33A권6호
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• pp.136-143
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• 1996

A simple analytic model for the planar junctions with multiple foating field limiting rings(FLR) is presented which yields analytic expressions for the breakdown voltage and optimum ring spacings. the normalized potential of each ring is derived as a function of the normalized depletion width and the ring spacing. Based on the assumption that the breakdwon occurs simulataneously at cylindrical junctions of FLR structure where the peak sruface electric fields are equal, the optimum ring spacings are determined. The resutls are in good agreement with the simulations obtained from two dimensional device simulation program MEDICI and with the experimental data reported. The normalized experessions allow a calculation of breakdown voltage and optimum spacing over a broad range of junction depth and background doping levels.

• 대한전자공학회논문지
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• 제21권1호
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• pp.45-50
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• 1984

결정면이 (100)인 실리콘 웨이퍼 위에 열확산(thermal diffusion)법을 이용하여 표면에 V형 흠이 형성된 N+P 태양전지를 제작하였다. (100) 실리콘 표면에 V형 홈을 형성시키기 위하여 이방성 부식용액으로는 etylendiamine, water, pyrocathecol 혼합용액을 사용하였다. 100mW/㎠의 조명아래에서 V형홈을 형성시킨 태양전지가 효율면에서 일반 평면 N+P 태양전지보다는 2.5∼3.5%, texturized 태양전지보다는 0.4∼0.6%정도의 증가를 보였다.

• Transactions on Electrical and Electronic Materials
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• 제6권1호
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• pp.1-5
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• 2005

Continued scaling of MOS devices requires the formation of the ultra shallow and very heavily doped junction. The simulation and experiment results show that the degradation of pMOS performance in logic and SRAM pMOS devices due to the excessive diffusion of the tail and a large amount of dose loss in the extension region. This problem comes from the high-temperature long-time deposition process for forming the spacer and the presence of fluorine which diffuses quickly to the $Si/SiO_{2}$ interface with boron pairing. We have studied the method to improve the pMOS performance that includes the low-energy boron implantation, spike annealing and device structure design using TCAD simulation.

• 한국정밀공학회지
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• 제22권2호
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• pp.194-201
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• 2005

Nanoscale fabrication of silicon substrate in an aqueous solution based on the use of atomic force microscopy was demonstrated. A specially designed cantilever with diamond tip, allowing the formation of damaged layer on silicon substrate easily by a simple scratching process (Tribo-Nanolithography, TNL), has been applied instead of conventional silicon cantilever for scanning. A slant nanostructure can be fabricated by a process in which a thin damaged layer rapidly forms in the substrate at the diamond tip-sample junction along scanning path of the tip and simultaneously the area uncovered with the damaged layer is being etched. This study demonstrates how the TNL parameters can affect the formation of damaged layer and the shape of 3-D structure, hence introducing a new process of AFM-based nanolithography in aqueous solution.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2010년도 제39회 하계학술대회 초록집
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• pp.294-294
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• 2010

Over the last decade, dye-sensitized solar cell (DSSC) has attracted much attention due to the high solar-to-electricity conversion efficiency up to 10% as well as low cost compared with p-n junction photovoltaic devices. DSSC is composed of mesoporous TiO2 nanoparticle electrodes coated with photo-sensitized dye, the redox electrolyte and the metal counter electrode. The performances of DSSC are dependent on constituent materials and interface as well as device structure. Replacing the heavy glass substrate with plastic materials is crucial to enlarge DSSC applications for the competition with inorganic based thin film photovoltaic devices. One of the biggest problems with plastic substrates is their low-temperature tolerance, which makes sintering of the photoelectrode films impossible. Therefore, the most important step toward the low-temperature DSSC fabrication is how to enhance interparticle connection at the temperature lower than $150^{\circ}C$. In this talk, the key issues for high efficiency plastic solar cells will be discussed, and several strategies for the improvement of interconnection of nanoparticles and bendability will also be proposed.