• International Journal of Highway Engineering
• /
• v.14 no.3
• /
• pp.173-182
• /
• 2012

Entry and exits of the rest area are sections where designed speed can be rapidly change and also a weak traffic safety section. In addition, two tasks can be performed simultaneously at entry of the rest area, particularly searching for deceleration and parking spaces/parking sides etc. Thus, design criteria is required in order to procure the stability of accessed vehicle. In case of Korea, geometric structure design criteria of entry facilities, such as toll-gate, interchange, junction etc was established. However there are no presence in a detailed standards for geometric structure of the rest area which affiliated road facilities. In this study, Derive problems in regards to the entry of geometric structure of resting areas by utilizing a sight survey and an investigation research of traffic accidents. The survey was targeting 135 general service areas. After Classifying the design section of resting areas' entry as well as derive design elements on each section, a speed measurement by targeting entry of rest areas and car behavior surveys were performed, then each element's minimum standard was derived through the analyses. According to the speeds at the starting/end point of entrance connector road, the minimum length of the entrance connector road is decided as 40m using Slowing-down length formula and based on the driving pattern, the range of the junction setting angle of the entrance connector road is defined as $12^{\circ}{\sim}17^{\circ}$. Suggest improvement plans for existing rest areas that can be applied realistically. This should be corresponded to the standards of entry and exit of developed rest areas.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.36 no.4
• /
• pp.413-417
• /
• 2023

Gallium Oxide (Ga₂O₃) is preferred as a material for next generation power semiconductors. The Ga₂O₃ should solve the disadvantages of low thermal resistance characteristics and difficulty in forming an inversion layer through p-type ion implantation. However, Ga₂O₃ is difficult to inject p-type ions, so it is being studied in a heterojunction structure using p-type oxides, such as NiO, SnO, and Cu₂O. Research the lateral-type FET structure of NiO/Ga₂O₃ heterojunction under the Gate contact using the Sentaurus TCAD simulation. At this time, the VG-ID and VD-ID curves were identified by the thickness of the Epi-region (channel) and the doping concentration of NiO of 1×10¹⁷ to 1×10¹⁹ cm-3. The increase in Epi region thickness has a lower threshold voltage from -4.4 V to -9.3 V at I_D = 1×10^-8 mA/mm, as current does not flow only when the depletion of the PN junction extends to the Epi/Sub interface. As an increase of NiO doping concentration, increases the depletion area in Ga₂O₃ region and a high electric field distribution on PN junction, and thus the breakdown voltage increases from 512 V to 636 V at I_D =1×10^-3 A/mm.

• Journal of Korean Association for Spatial Structures
• /
• v.12 no.4
• /
• pp.109-118
• /
• 2012

The large-space single-layer lattice dome is relatively simpler in terms of the arrangement of the various framework members and of the design of the junction than the multi-layered lattice dome, can reduce the numbers and quantity of the framework members, and has the merit of exposing the beauty of the framework as it stands. The single-layer lattice dome, however, requires a stability investigation of the whole structure itself, along with an analysis of the stress of the framework members, because an unstable phenomenon called "buckling" occurs when its weight reaches critical levels. Many researchers have systematically conducted researches on the stability evaluation of the single-layer lattice dome. No construction case of a single-layer lattice dome with a 300-m-long span, however, has yet been reported anywhere in the world. The large-space dome structure is difficult to erect due to the gigantic span and higher ceiling compared with other common buildings, and its construction cost is generally huge. The method of erecting a structure causes major differences in the construction cost and period. Therefore, many researchers have been conducting various researches on the method of erecting such structure. The step-up method developed by these authors can reduce the construction cost and period to a great extent compared with the other general methods, but the application of this method inevitably requires the development of system supports in the center section as well as pre-existing supports in the boundary sections. In this research, the safety during the construction of a single-layer lattice dome with 300-m-long span using pre-existing materials was examined in the aspect of structural strength, and the basic data required for manufacturing the supports in the application of the step-up method developed by these authors during the erection of the roof structure were obtained.

• Journal of Magnetics
• /
• v.11 no.1
• /
• pp.25-29
• /
• 2006

Recent experiments have demonstrated high TMR ratios in MTJs with the MgO barrier [1,2]. The CoFeB/MgO/CoFeB junctions showed better properties than the CoFe/MgO/CoFe junctions because the MgO layer had a good crystalline structure with (001) texture and smooth and sharp interface between CoFeB/MgO [3]. The amorphous CoFeB with 20 at%B starts the crystallization at $340^{\circ}C$ [4] and this crystallization of the CoFeB helps obtaining the high TMR ratio. In this work, the compositional changes in the MgO barrier and at the interface of CoFeB/MgO/CoFeB after the CoFeB crystallization were studied in annealed MTJs. XPS depth profiles were utilized. TEM analyses showed that the MgO barrier had (100) texture on CoFeB in the junctions. B in the bottom CoFeB layer diffused into the MgO barrier and B-oxide was formed at the interface of CoFeB/MgO/CoFeB after the CoFeB crystallization.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.27 no.4B
• /
• pp.388-396
• /
• 2002

In this paper, An aperture-coupled microstrip patch antenna operating at WLL frequency range(Rx : 2.3∼2.33Ghz, Tx : 2.37 ∼2.4Ghz) for WLL repeater is designed and fabricated. FR-4 epoxy substrate with 4.7 relative permittivity is inserted between feed-line and patch plane. Aperture-coupled structure is employed for consideration of bandwidth improvement and gain\`s characteristics. Air gap is arranged at each layer for bandwidth extension and radome is used as a protector in the upper patch. In this paper, both 1 port and 2 port are designed as 1$\times$2 array antenna which uses T-junction and λ$\_$g//4 transformer. Here, 1 port is used as transmitting/receiving antenna and 2 port is used as receiving antenna. Functionally independent two antennas using space diversity arrange slots between two antennas in order to be placed at the same place. As a result, we obtained a excellent isolation below -40dB and return loss is reduced by means of slots arrangement between patch and antenna.

• 한국신재생에너지학회:학술대회논문집
• /
• 2005.06a
• /
• pp.113-116
• /
• 2005

In this paper, silicon thin-film solar cells(Si- TFSC) and a-Si/c-Si heterojunction solar cells(HJ-cell) are investigated. The Si-TFSC was prepared on glass substrate by depositing $1-3{\mu}m$ thin-film silicons by glow discharge method. The $a-Si:H/{\mu}c-Si:H$ tandem solar cells on textured ZnO:A1 TCO (transparent conducting oxide) showed improved Jsc in top and bottom cells than that on $SnO_2:F$ TCO. This enhancement of jsc resulted from improved light trapping effect by front textured ZnO:A1. The a-Si/c-Si HJ-cells with simple structure without high efficiency features are suffering from low Voc and Jsc. The improvement of front nip and back interface properties by adopting high quality silicon-films at low temperature should be done both for increasing device performances and production cost.

• The Transactions of the Korean Institute of Electrical Engineers P
• /
• v.61 no.2
• /
• pp.97-102
• /
• 2012

CPV system in the desert areas or areas near the equator, as is suitable for high-temperature region. As compared to silicon solar cells, CPV system have a high proportion of a BOS (balance of system). Solar cells because of its low proportion when designing a module technology is applied in a variety of ways. Applied to the CPV system is classified into two kinds of optical technology. One of those using fresnel lens uses refraction of light energy. The other is a mirror reflection of the structure using sprays. Both of these two ways to condense the sun to collect solar cell is a form of light. And goals by using a small solar cell materials is to produce more energy. In this paper, suitable for a domestic environment, with the aim CPV Manufacturing Technology, built on a variety of modular process technology to the development of a prototype performance analysis was carried out. In particular, silicone coated on the glass by the method of implementation of the Fresnel lens SOG(Silicon on glass) by applying the lens to absorb the solar spectrum was broad. In addition to, for the analyze to characteristics of the CPV module, developed CPV module performance and generating characteristics studied. These related technology through research and development of high-performance multi-junction solar cells, modules, development of concentrating solar power systems to facilitate the growth of the market is considered to be.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.45 no.8
• /
• pp.1-10
• /
• 2008

In this paper, we describe a design of a 128bit MRAM based on a new switching architecture which is Local Field Switching(LFS). LFS uses a local magnetic field generated by the current flowing through an MTJ. This mode reduces the writing current since small current can induce large magnetic field because of close distance between MTJ and the current. It also improves the cell selectivity over using conventional MTJ architecture because it doesn't need a digit line for writing. The MRAM has 1-Transistor 1-Magnetic Tunnel Junction (IT-1MTJ) memory cell structure and uses a bidirectional write driver, a mid-point reference cell block and a current mode sense amplifier. CMOS emulation cell is adopted as an LFS-MTJ cell to verify the operation of the circuit without the MTJ process. The memory circuit is fabricated using a $0.18{\mu}m$ CMOS technology with six layers o) metal and tested on custom board.

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.47 no.7
• /
• pp.128-134
• /
• 2010

In this paper, a high-power 20-way stripline power divider with low insertion loss and low side lobe level is successfully designed, fabricated and measured as a feed network for an S-band linear array antenna having Dolph-Chebyshev current distribution which has a narrow beam width and very low side lobe level (SLL). The 20-way stripline power divider consists of an 8-way power divider, three 4-way power dividers and three ring hybrids. It utilizes a T-junction structure as a basic element for power dividing. Notches and modified input/output N-to-stripline transitions are used for improving insertion loss and return loss. The fabricated power divider shows insertion loss less than 0.3 ㏈ and rms phase mismatch less than 8o in the full bandwidth. A final 40-way power divider is synthesized by combining symmetrically two 20-way power dividers and is expected to have SLL over 40 dB, based on the measured results of the 20-way power divider.

• Journal of the Korean Institute of Telematics and Electronics D
• /
• v.36D no.11
• /
• pp.45-55
• /
• 1999

The small signal analyzer for the stationary drift-diffusion equation is developed. The slotboom variables of the potential, electron and hole concentrations for the response of applied small signal are defined and the stationary drift-diffusion equation is linearlized on DC operation point by $S^3A$ method. Frontal solver, which is used to solve the global matrix, progresses the accuracy of the solution in high frequency and minimizes the requirement of the memory. The simulations are executed on the structure of 3 dimensional N'P junction diode and 2 dimensional n-MOSFET to verify the proposed algorithm. The average relative errors of the conductance and the capacitance compared with MEDICI are about 26% and 0.67 for N'P junction diode and 7.75% and 2.24% for n-MOSFET. The simulation by the proposed algorithm can analyze the stationary drift-diffusion equation for applied small signal in high frequency region about 100GHz.