• The Journal of Korean Institute of Communications and Information Sciences
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• 제25권8B호
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• pp.1493-1498
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• 2000

In this paper, we introduce a modified interference cancellation scheme to overcome MAI in DS-CDMA. Among ICs(Interference Cancellers), PIC(Parallel IC) requires the more complexity, and SIC(Successive IC) faces the problems of the long delay time. Most of all, the adaptive detector achieves the good BER performance using the adaptive filter conducted iteration algorithm. so it requires many iterations. To resolve the problems of them, we propose an improved adaptive detector that the received signal removed MAI through the sorting scheme and the cancellation method are fed into the adaptive filter. Because the improved input signal is fed into the adaptive filter, it has the same BER performance only using smaller iterations than the conventional adaptive detector, and the proposed detector having adaptive filter requires less complexity than the other detectors.

• Journal of Korean Society of Industrial and Systems Engineering
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• 제38권3호
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• pp.56-63
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• 2015

Several fields of science have demanded large-scale workflow support, which requires thousands of CPU cores or more. In order to support such large-scale scientific workflows, high capacity parallel systems such as supercomputers are widely used. In order to increase the utilization of these systems, most schedulers use backfilling policy: Small jobs are moved ahead to fill in holes in the schedule when large jobs do not delay. Since an estimate of the runtime is necessary for backfilling, most parallel systems use user's estimated runtime. However, it is found to be extremely inaccurate because users overestimate their jobs. Therefore, in this paper, we propose a novel system for the runtime prediction based on workload-aware clustering with the goal of improving prediction performance. The proposed method for runtime prediction of parallel applications consists of three main phases. First, a feature selection based on factor analysis is performed to identify important input features. Then, it performs a clustering analysis of history data based on self-organizing map which is followed by hierarchical clustering for finding the clustering boundaries from the weight vectors. Finally, prediction models are constructed using support vector regression with the clustered workload data. Multiple prediction models for each clustered data pattern can reduce the error rate compared with a single model for the whole data pattern. In the experiments, we use workload logs on parallel systems (i.e., iPSC, LANL-CM5, SDSC-Par95, SDSC-Par96, and CTC-SP2) to evaluate the effectiveness of our approach. Comparing with other techniques, experimental results show that the proposed method improves the accuracy up to 69.08%.

• Journal of the Institute of Electronics Engineers of Korea SC
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• 제41권6호
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• pp.17-25
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• 2004

In this paper, we propose a new small swing domino logic for low-power consumption. To reduce the power consumption, both the precharge node and the output node swing the range from 0 to $V_{REF}$- $V_{THN}$, where $V_{REF}$=VDD-n $V_{THN}$ (n=1, 2, and 3). This can be done by adding the inverter structure on domino logic that allows a full swing or a small swing on its input terminal without leakage current. Compared to previous works, the proposed structure can save the power consumption of more than 30% for n=0, 1, 2, and 3 in the equation of $V_{REF}$=VDD-n $V_{THN}$. A multiplier applying the proposed domino logic has been designed and fabricated using a 0.35-${\mu}{\textrm}{m}$ n-well CMOS process under 3.3-V supply voltage. Compared with other previous works, it shows a 30% power reduction and a better feature in power-delay product.lay product.

• Korean Journal of Optics and Photonics
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• 제17권2호
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• pp.175-180
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• 2006

A single sideband(SSB) modulator operating at 5.5 GHz was fabricated by polarization inversion techniques. The dimension of domain inversion in a $LiINbO_3$ Mach-Zehnder structure was precisely controlled so that the RF signal applied on two Mach-Zehnder arms gives rise to $90^{\circ}$ effective phase difference. The single sideband suppression was maximized by optimization of the polarization status of the optical input and by the DC bias value. The fabricated device showed the center frequency of 5.8 GHz and the maximum sideband suppression of 33dB, where the bandwidth of 15 dB sideband suppression ranged over a 2.5 GHz span. The optical phase delay could be regulated by the DC bias voltage, fur example, the enhanced optical modulation sideband was distinctively switched from the upper sideband to the lower sideband by changing the DC bias voltage from 1.9 V to -10.6 V.

• The Journal of Korean Institute of Communications and Information Sciences
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• 제27권6C호
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• pp.625-631
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• 2002

This paper presents a MSB-first digit-serial systolic array for computing modular multiplication of A(x)B(x) mod G(x) in finite fields $GF(2^m)$. From the MSB-first multiplication algorithm in $GF(2^m)$, we obtain a new data dependence graph and design an efficient digit-serial systolic multiplier. For circuit synthesis, we obtain VHDL code for multiplier, If input data come in continuously, the implemented multiplier can produce multiplication results at a rate of one every [m/L] clock cycles, where L is the selected digit size. The analysis results show that the proposed architecture leads to a reduction of computational delay time and it has much more simple structure than existing digit-serial systolic multiplier. Furthermore, since the propose architecture has the features of unidirectional data flow and regularity, it shows good extension characteristics with respect to m and L.

• The Journal of Korean Institute of Communications and Information Sciences
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• 제33권5C호
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• pp.395-402
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• 2008

In this paper, an I/Q channel 12bits 40MS/s Pipeline Analog to Digital Converter that is able to apply to WLAN/WMAN system is proposed. The proposed ADC integrates DLL based duty-correction circuit which corrects the fluctuations in the duksty cycle caused by miniaturization of CMOS devices and faster operating speeds. It is designed as a 1% to 99% input clock duty cycle could be corrected to 50% output duty cycle. The prototype ADC is implemented in a $0.18{\mu}m$ CMOS n-well 1-poly 6-metal process and dissipates 184mW at 1.8V single supply The SNDR of the proposed 12bit ADC is 52dB and SFDR of 59dBc(@Fs=20MHz, Fin=1MHz) is measured.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• 제12권7호
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• pp.1086-1093
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• 2001

A new linearization technique for RF high-power amplifiers(HPAs) using n-th order error signal generator (ESGn) is proposed. The n-th order ESG generates an error signal based on the complex envelope transfer characteristics of the HPA, which is combined at the output of the HPA. Therefore, the higher-order nonlinearlities are not affected by the ESG$\_$n/ and the stability of the linearized system is guaranteed due to the inherent open-loop configuration. Moreover, the output delay loss can be avoided, because the error signal is generated with the input signal of the HPA. The IMD(intermodulation distortion) improvement obtained applying the ESG$\_$7/ to 5 W class A HPA in cellular band demonstrates the feasibility of the proposed postdistortion system.

• The Transactions of the Korea Information Processing Society
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• 제4권10호
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• pp.2485-2492
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• 1997

Nowadays the traffic conditions have been getting worse due to continuous increase in the number of vehicles. So it has become more important to manage traffic signal lights efficiently. Recently fuzzy logic is introduced to control the cycle time of traffic lights adaptively. Conventional fuzzy logic controller adjusts the extension time of current green phase by using the fuzzy input variables such as the number of entering vehicles at the green light and the number of waiting vehicle during the red light. However this scheme is inadequate for an intersection with variable traffic densities. In this paper, a new FLC with asymmetric membership functions that reflects more exactly traffic flows than other FLCs with symmetric ones regardless of few control rules is propsed. The effectiveness of the proposed method was shown through simulation of a single intersection. The experimental results yielded the superior performance of the proposed FLC in terms of the average delay time, the number of passed vehicles, and the degree of saturation.

• Structural Engineering and Mechanics
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• 제76권4호
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• pp.465-477
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• 2020

This paper presents an investigation on the dynamic behavior of SRC columns with built-in cross-shaped steels under impact load. Seven 1/2 scaled SRC specimens were subjected to low-speed impact by a gravity drop hammer test system. Three main parameters, including the lateral impact height, the axial compression ratios and the stirrup spacing, were considered in the response analysis of the specimens. The failure mode, deformation, the absorbed energy of columns, as well as impact loads are discussed. The results are mainly characterized by bending-shear failure, meanwhile specimens can maintain an acceptable integrity. More than 33% of the input impact energy is dissipated, which demonstrates its excellent impact resistance. As the impact height increases, the flexural cracks and shear cracks observed on the surface of specimens were denser and wider. The recorded time-history of impact force and mid-span displacement confirmed the three stages of relative movement between the hammer and the column. Additionally, the displacements had a notable delay compared to the rapid changes observed in the measured impact load. The deflection of the mid-span did not exceed 5.90mm while the impact load reached peak value. The impact resistance of the specimen can be improved by proper design for stirrup ratios and increasing the axial load. However, the cracking and spalling of the concrete cover at the impact point was obvious with the increasing in stiffness.

• Proceedings of the Korean Society of Propulsion Engineers Conference
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• 한국추진공학회 2008년 영문 학술대회
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• pp.330-339
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• 2008

Ground-based interceptors(GBI) comprise a major element of the strategic defense against hostile targets like Intercontinental Ballistic Missiles(ICBM) and reentry vehicles(RV) dispersed from them. An optimum design of the subsystems is required to increase the performance and reliability of these GBI. Propulsion subsystem design and optimization is the motivation for this effort. This paper describes an effort in which an entire GBI missile system, including a multi-stage solid rocket booster, is considered simultaneously in a Genetic Algorithm(GA) performance optimization process. Single goal, constrained optimization is performed. For specified payload and miss distance, time of flight, the most important component in the optimization process is the booster, for its takeoff weight, time of flight, or a combination of the two. The GBI is assumed to be a multistage missile that uses target location data provided by two ground based RF radar sensors and two low earth orbit(LEO) IR sensors. 3Dimensional model is developed for a multistage target with a boost phase acceleration profile that depends on total mass, propellant mass and the specific impulse in the gravity field. The monostatic radar cross section (RCS) data of a three stage ICBM is used. For preliminary design, GBI is assumed to have a fixed initial position from the target launch point and zero launch delay. GBI carries the Kill Vehicle(KV) to an optimal position in space to allow it to complete the intercept. The objective is to design and optimize the propulsion system for the GBI that will fulfill mission requirements and objectives. The KV weight and volume requirements are specified in the problem definition before the optimization is computed. We have considered only continuous design variables, while considering discrete variables as input. Though the number of stages should also be one of the design variables, however, in this paper it is fixed as three. The elite solution from GA is passed on to(Sequential Quadratic Programming) SQP as near optimal guess. The SQP then performs local convergence to identify the minimum mass of the GBI. The performance of the three staged GBI is validated using a ballistic missile intercept scenario modeled in Matlab/SIMULINK.