• Journal of information and communication convergence engineering
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• v.9 no.6
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• pp.729-732
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• 2011

Power consumption during testing System-On-Chip (SOC) is becoming increasingly important as the IP core increases in SOC. We present a new algorithm to reduce the scan-in power using the modified scan latch reordering and clock gating. We apply scan latch reordering technique for minimizing the hamming distance in scan vectors. Also, during scan latch reordering, the don't care inputs in scan vectors are assigned for low power. Also, we apply the clock gated scan cells. Experimental results for ISCAS 89 benchmark circuits show that reduced low power scan testing can be achieved in all cases.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.10
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• pp.173-184
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• 1994

BiCMOS circuits mixed with CMOS and bipolar technologies show peculiar fault characteristics that are different from those of other technoloties. It has been reported that because most of short faults in BiCMOS circuits cause logically intermediate level at outputs, current monitoring method is required to detect these faluts. However current monitoring requires additional hardware capabilities in the testing equipment and evaluation of test responses can be more difficult. In this paper, we analyze the characteristics of faults in BiCMOS circuit together with their test methods and propose a new design technique for testability to detect the faults by logic monitoring. An effective method to detect the transition delay faults induced by performance degradation by the open or short fault of bipolar transistors in BiCMOS circuits is presented. The proposed design-for-testability methods for BiCMOS circuits are confirmed by the SPICE simulation.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.51 no.5
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• pp.242-248
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• 2002

It is important to develop new effective technologies to increase the interruption capacity and to reduce the size of a UB(Gas Circuit Breakers). Major design parameters such as nozzle geometries and interrupting chamber dimensions affect the cooling of the arc and the breaking performance. But it is not easy to test real GCB model in practice as in theory. Therefore, a simulation tool based on a computational fluid dynamics(CFD) algorithm has been developed to facilitate an optimization of the interrupter. Special attention has been paid to the supersonic flow phenomena between contacts and the observation of hat-gas flow for estimating the breaking performance. However, there are many difficult problems in calculating the flow characteristics in a GCB such as shock wave and complex geometries, which may be either static or in relative motion. Although a number of mesh generation techniques are now available, the generation of meshes around complicated, multi-component geometries like a GCB is still a tedious and difficult task for the computational fluid dynamics. This paper presents the CFD program using CFB-CAD integration technique based on Cartesian cut-cell method, which could reduce researcher's efforts to generate the mesh and achieve the accurate representation of the geometry designed by a CAD tools.

• Corrosion Science and Technology
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• v.6 no.3
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• pp.103-111
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• 2007

The effect of stress factors on the growing process of stress corrosion cracking (SCC) of the sensitized 18-8 stainless steel in high temperature water was investigated using equations of crack growth rate derived from applying electric circuits to SCC corrosion paths. Three kinds of cross sections have to be considered when electric circuit is constructed using total current. The first is ion flow passage area, $S_{sol}$, of solution in crack, the second is total dissolving surface area, $S_{dis}$, of metal on electrode of crack tip and the third is dissolving cross section, $S_{met}$, of metal on grain boundary or in base metal or in welding metal. Stress may affect each area. $S_{sol}$ may depend on applied stress, $\sigma_{\infty}$, related with crack depth. $S_{dis}$ is expressed using a factor of $\varepsilon(K)$ and may depend on stress intensity factor, K only. SCC crack growth rate is ordinarily estimated using a variable of K only as stress factor. However it may be expected that SCC crack growth rate depends on both applied stress $\sigma_{\infty}$ and K or both crack depth and K from this consideration.$\varepsilon(K)$ is expressed as ${\varepsilon}(K)=h_2{\cdot}K^2+h_3{\cdot}K^3$ when $h_{2}$ and $h_{3}$ are coefficients. Also, relationships between SCC crack growth rate, da/dt and K were simulated and compared with the literature data of JBWR-VIP-04, NRC NUREG-0313 Rev.2 and SKIFS Draft. It was pointed out in CT test that the difference of distance between a point of application of force and the end of starter notch (starting point of fatigue crack) may be important to estimate SCC crack growth rate. An anode dissolution current density was quantitatively evaluated using a derived equation.

• Journal of IKEEE
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• v.9 no.1 s.16
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• pp.57-64
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• 2005

This paper presents a built-in current sensor(BICS) that detects defects in CMOS integrated circuits using the current testing technique. This circuit employs a cross-coupled connected PMOS transistors, it is used as a current comparator. The proposed circuit has a negligible impact on the performance of the circuit under test (CUT) and high speed detection time. In addition, in the operation of the normal mode, the BlCS does not have dissipation of extra power, and it can be applied to the deep submicron process. The validity and effectiveness are verified through the HSPICE simulation on circuits with defects. The area overhead of a BlCS versus the entire chip is about 9.2%. The chip was fabricated with Hynix $0.35{\mu}m$ 2-poly 4-metal N-well CMOS standard technology.

• Proceedings of the KIEE Conference
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• 2011.07a
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• pp.1041-1042
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• 2011

저압 차단기의 단락성능평가를 위한 단락시험설비의 측정시스템은 고전압, 대전류를 안전하고 정밀하게 측정하기 위해 여러 가지 측정기들로 시스템으로 구성되어 있으며, 시험 신뢰도의 확보를 위해 측정불확도에 대한 평가가 이루어져야 한다. 본 논문에서는 표준 Shunt와 비교시험을 통하여 전류 측정 시스템의 측정불확도를 추정하고자 한다.

• Journal of the Korean Institute of Telematics and Electronics
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• v.25 no.4
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• pp.417-421
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• 1988

In order to analyze the blooming suppression mechanism of a MOS image sensor, test photodiodes have been fabricated and characterized by attaching a source follower circuit. The blooming suppression ability of npn structure compared to that of np structure is quantitatively analyzed and measured by experiment. The dependency of the blooming current on the substrate voltage, the vertical MOS gate voltage and the video voltage is measured and the optimum condition for blooming suppression is presented.

• Proceedings of the IEEK Conference
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• 2002.06e
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• pp.117-120
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• 2002

This paper is to develop the sensing system for opening-force measurement such as O-Ring muscular meridian. We designed to overcome the functional limit that the conventional force-sensor can measure just the closing-force. Therefore, the new sensor can meet a variety of application as well as O-Ring test. The structure of the new sensor is an actuator-type system using an electromagnet. That is made up of mechanical system, electromagnet, current transformer and computer interface circuit. Driving software and user interface program of the new sensor system also is explained in this paper.

• Proceedings of the KIEE Conference
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• 2001.04a
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• pp.455-458
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• 2001

This paper presents an axial flux permanent magnet synchronous generator with a high power-to-weight ratio, dedicated for small-scale gearless wind power generation plants. For this purpose, a specific design is necessary to meet the imposed requirements. In this paper the design technique for the specifications is presented. The aim of the paper is also to discuss some of the first obtained test results and the involved demagnetizing problem (i.e. short-circuit).

• Proceedings of the KIEE Conference
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• 1994.07a
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• pp.60-62
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• 1994

In this paper, the LVDT with compensating secondary coil and secondary current boost circuit is proposed. The LVDT was experiment with a test device, and analyzed with numerical method (FEM), It is shown that the LVDT has a good linearities for the measurement of the displacement and position, etc..