• Journal of the Korea Institute of Information and Communication Engineering
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• v.7 no.1
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• pp.100-105
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• 2003

In this paper, we propose the novel test method effectively to detect short and open faults in CMOS op-amp. The proposed method uses a sinusoidal signal with higher frequency than unit gain bandwidth. Since the proposed test method doesn't need complex algorithm to generate test pattern, the time of test pattern generation is short, and test cost is reduced because a single test pattern is able to detect all target faults. To verify the proposed method, CMOS two-stage operational amplifier with short and open faults is designed and the simulation results of HSPICE for the circuit have shown that the proposed test method can detect short and open faults in CMOS op-amp.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.14 no.2
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• pp.14-23
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• 2015

This study was intended to evaluate the feasibility of the vehicle detector using a coil sensor. For the evaluation, the research team built a test environment for the detector consisting of a oscillation circuit, data collecting circuit, data monitoring and saving circuit, etc. As the result of the frequency analysis of the detector from the test environment, it was verified for the detector using a coil sensor to generate stable frequencies. In addition, the ease of construction and management was tested by comparing the size of cutting areas, consumption of installation materials, and installation time for a traditional loop detector and the detector using a coil sensor. As a result, the installation of the detector using a coil sensor requires less size of cutting areas, consumption of installation materials, and installation time.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.3
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• pp.555-562
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• 2008

In this paper we proposed a practical low-power design technique using clock-gating in RTL. An efficient low-power methodology is that a high-level designer analyzes a generic system and designs a controller for clock-gating. Also the desirable flow is to derive clock-gating in normal synthesis process by synthesis tool than to insert directly gate to clock line. If low-power is considered in coding process, clock is gated in coding process. If not considered, after analyzing entire operation. clock is Bated in periods of holding data. After analyzing operation for clock-gating, a controller was designed for it, and then a low-power circuit was generated by synthesis tool. From result, we identified that the consumed power of register decreased from 922mW to 543mW, that is the decrease rate is 42%. In case of synthesizing the test circuit using synthesizer of Power Theater, it decreased from 322mW to 208mW (36.5% decrease).

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.48 no.5
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• pp.257-263
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• 1999

Recently the performance of CO2 arc welding machine has been advanced significantly through the adoption of inverter circuit topology which made it possible to control the waveform of welding current and thus to suppress the spatter generation. However, the optimum waveform is still uncertain. As a first step for figuring out the promising waveforms, this study was performed to set-up the experimental system for studying the effect of waveform variables, The system designed in this study is a digital controller using single chip microprocessor of 80C196KC. As a result of performance test of this system, it was demonstrated all of the waveform variables could be set individually and the resultant waveforms appeared to be pretty much the same as the intended one.

• Journal of Drive and Control
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• v.9 no.4
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• pp.58-61
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• 2012

The customers who used the hydroulic system desire the product that has more detailed specification quickly during the industrial technology is developed. Every researcher try to reduce the developed period and to satisfy the customers' desire. Lot's of simulation software and hardware already was used to be satisfied those purpose. But these kind of equipment need a lot of cost to set up and technical knowledge to drive that system. This paper concerns about analog PID controller that can be assembled with a few resistor, condenser and optional amplifier and doesn't need technical knowledge to drive. At the first, the plant was modeled mathematically to design the analog PID controller's circuit. After that, PID controller's parameter was selected by customers' desire. Finally, the analog PID controller's circuit was assembled from the control law. The circuit's availability was confirmed by step response test in the controlled system.

• Journal of Power Electronics
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• v.15 no.1
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• pp.246-255
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• 2015

This paper presents experimental results and its assessment of a variable-speed wind power generation system (VSWPGS) using permanent magnet synchronous generator (PMSG) and boost chopper circuit (BCC). Experimental results are obtained by a test bench with a wind turbine emulator (WTE). WTE reproduces the behaviors of a windmill by using servo motor drives. The mechanical torque references to drive the servo motor are calculated from the windmill wing profile, wind velocity, and windmill rotational speed. VSWPGS using PMSG and BCC has three speed control modes for the level of wind velocity to control the rotational speed of the wind turbine. The control mode for low wind velocity regulates an armature current of generator with BCC. The control mode for middle wind velocity regulates a DC link voltage with a vector-controlled inverter. The control mode for high wind velocity regulates a pitch angle of the wind turbine with a pitch angle control system. The hybrid of three control modes extends the variable-speed range. BCC simplifies the maintenance of VSWPGS while improving reliability. In addition, VSWPGS using PMSG and BCC saves cost compared with VSWPGS using a PWM converter.

• Proceedings of the KIEE Conference
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• 1995.07a
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• pp.30-32
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• 1995

The model interrupters of $SF_6$ gas electromagnetic contactor whose ratings are the voltage of 7.2kV and the short circuit current of 4.0kA have been designed and manufactured on the basis of theoretical and computational analysis for its development. The eddy current analysis, the magnetic field analysis and the calculation of the rotational force on arcs have been conducted using FLUX2D package. The short circuit current interrupting tests have been conducted to the model interrupters using the simplified capacitive synthetic test circuit in KERI. The results show that the model interrupters have a sufficient interrupting capability and the new design concept is proper for a good interrupting performance.

• Progress in Superconductivity and Cryogenics
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• v.6 no.3
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• pp.50-55
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• 2004

We fabricated and tested a resistive type superconducting fault current limiter (SFCL) of three-phase 6.6 $kV_{rms}/200 A_{rms}$ rating based on YBCO thin films grown on sapphire substrates with a diameter of 4 inches, Short circuit tests were carried out at a accredited test facility for single line-to- ground faults, phase-to-phase faults and three-phase faults, Each phase of the SFCL was composed of 8${\times}$6 elements connected in series and parallel respectively. Each element was designed to have the rated voltage of 600 $V_{rms}$. A NiCr shunt resistor of 23 Ω was connected to each element for simultaneous quenches. Firstly, single phase-to-ground fault tests were carried out. The SFCL successfully developed the impedance in the circuit within 0.12 msec after fault and controlled the fault current of 10 $kA_{rms} below 816 A_{peak}$ at the first half cycle. In addition, in case of phase-to-phase fault and three- phase fault test. simultaneous quenches among the SFCLs of the phases successfully accomplished. In conclusion. the SFCL showed excellent performance of current limitation upon fault and stable operation regardless of the amplitude of fault currents.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.34 no.1
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• pp.43-48
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• 2010

The heat sink system for a main board in a network server computer is built on printed circuit board by an anchor structure, mounted by eutectic SnPb solder. The solder creeping is caused by a constant high temperature condition in the computer and it eventually makes fatal failures. The FE model is used to calculate the stress and predict the life of soldered anchor in the computer. In the model, Anand constitutive equation is employed to simulate creep characteristics of solder. The creep test is conducted to verify and calibrate the solder model. A special jig is designed to mitigate the flexure of printed circuit board and to get the creep deformation of solder only in the test. Test results are compared with analysis and calibration is conducted on Anand model's constants. Precise life prediction of soldered anchor in creep condition can be performed by this model.

• Proceedings of the KIEE Conference
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• 2002.11d
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• pp.131-134
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• 2002

The optimum design technology using combind F.E.M and eauivalent circuit is so fast and accurate that it can be applied to the optimum rotor design of an inverter-fed induction motor in high efficiency motor making industry. The optimum characteristics fer a rotor slot model of a 3 phase inverter-134 nduction motor was previously verified by a time-step F.E.M. In this paper, four verification models with the design variables near the optimum point are designed to chech whether the characteristics of a slot model presented is not less than those of the near models. The outputs of whole models are analyzed in a time-step Finite Element Method and compared in the experimental test. The economical and efficient selecting method of design variables fur the computer simulation and experimental test is presented in order to assure the optimum point.