• Journal of Biomedical Engineering Research
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• v.4 no.1
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• pp.9-14
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• 1983

A new quantitative method was developed for separation of three interactive physiological factors (hepatic glucose balance, peripheral tissue's insulin resistivity, and insulin secretion rate) influencing glucose intolerance in diabetic mellitus using an equivalent circuit model and the intravenous glucose tolerance test (IVGTT) in six dogs and twenty two humans. The results show that the estimated model parameters of the above three factors are useful for evaluating different glucose-insulin kinetics in normal and diabetic subjects.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.48 no.2
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• pp.117-126
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• 1999

The environmental impact of the KEPCO 765-kV transmission line was studied using a full scale test line in order to develop the design technology. Therefore this paper describes an environmental design summary of the audible noise, hum noise, wind noise, radio interference, TV interference and electric field measurement from the KEPRI 765-kV double circuit transmission test line with a bundle of $6-480mm^2$ conductors per phase. The analysis of the test results shows that 6-Rail and 6-Cardinal conductors bundle satisfy the audible noise criterion & TV interference under the stable rainy weather condition and the radio interference level under the fair weather. And the other items are also agreed with the design level criterion for KEPCO 765-kV transmission line.

• Journal of Korea Multimedia Society
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• v.4 no.6
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• pp.570-578
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• 2001

Boundary scan architecture test methodology was introduced to facilitate the testing of complex printed circuit board. The boundary scan architecture has a tremendous potential for real time monitoring of the operational status of a system without interference of normal system operation. In this paper, a new type of embedded controller for real time monitoring of the operational status of a system is proposed and designed by using boundary scan architecture. The proposed real time monitoring embedded controller consists of test access port controller and an embedded controller proposed real time monitoring embedded controller using boundary scan architecture can save the hard-wire resource and can easily interface with boundary scan architecture chip. Experimental results show that the real time monitoring using proposed embedded controller is more effective then the real time monitoring using host computer.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2017.10a
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• pp.53-54
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• 2017

In this paper, we have studied the electrostatic discharge test for the battery protection circuit module in the lithium ion battery used as a smartphone battery which is used to prevent the explosion hazard due to overcharge, over discharge, and short-circuit. A lithium ion battery of S company was used as an experimental sample, and an ESD gun simulator compliant with IEC 61000-4-2 standard was used for electrostatic discharge injection. The contact discharge was applied to the various pins of the battery protection circuit module in increments of 2 kV in the range of 2 kV to 10 kV and in 5 kV increments in the range of 10 kV to 30 kV.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.9
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• pp.71-79
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• 1993

This paper proposes a new test pattern generation methodology for combinational logic circuits using neural networks based on a modular structure. The CUT (Circuit Under Test) is described in our gate level hardware description language. By conferring neural database, the CUT is compiled to an ATPG (Automatic Test Pattern Generation) neural network. Each logic gate in CUT is represented as a discrete Hopfield network. Such a neual network is called a gate module in this paper. All the gate modules for a CUT form an ATPG neural network by connecting each module through message passing paths by which the states of modules are transferred to their adjacent modules. A fault is injected by setting the activation values of some neurons at given values and by invalidating connections between some gate modules. A test pattern for an injected fault is obtained when all gate modules in the ATPG neural network are stabilized through evolution and mutual interactions. The proposed methodology is efficient for test generation, known to be NP-complete, through its massive paralelism. Some results on combinational logic circuits confirm the feasibility of the proposed methodology.

• Journal of the Korean Institute of Navigation
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• v.22 no.4
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• pp.45-50
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• 1998

A recently constructed commercial ship is a complexive integrated system like a small city in which has a generator, power distributing facilities, various radio equipments and high power circuit breakers are installed. Therfore it could make a malfunction of the microprocessor in the various control units which are so important during the ocean voyage of larger ship. This paper has studied whether is properly required or not on the view of the actual electro magnetic compatibility status on the electromagnetic interference and suceptibility test requirments listed on the IACS (International Association of the Classification Society). Through these results, we are looking forward to the new suggestions of the Electro Magnetic Compatibility test in order to reduce the malfunction in the ship regarding test item, test level, and test condition.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.15 no.11
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• pp.6821-6829
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• 2014

The use of semiconductor devices as a component of eco-friendly motor vehicles has increased and their widespread use as high voltage switches is expected. On the other hand, in the case of high-voltage switches, reliability test equipment is not localized. To test high voltage switches, this paper analyzed the relevant test standards for developing power supplies. In particular, for the automotive semiconductor reliability test, the AEC (Automotive Electronic Council) Q101 was analyzed. Based on that, the standard specifications of the power supply were determined. For the main power circuit, the pull bridge converter was adopted and based on the specification, the circuit parameters were determined and verified by simulation. The interface for the parallel and pattern operation was designed. The characteristics of the power supply were tested.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.8
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• pp.29-35
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• 2010

In this paper we propose a new pattern generator for a BIST architecture that can reduce the power consumption during test application. The principle of the proposed method is to reconstruct an LFSR circuit to reduce WSAs of the heavy nodes by suppressing the heavy inputs. We propose algorithms for finding heavy nodes and heavy inputs. Using the Modified LFSR which consists of some AND/OR gates trees and an original LFSR, BIST applies modified test patterns to the circuit under test. The proposed BIST architecture with small hardware overhead effectively reduces the average power consumption during test application while achieving high fault coverage. Experimental results on the ISCAS benchmark circuits show that average power reduction can be achieved up to 30.5%.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.9
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• pp.26-34
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• 1998

This paper presents a characterization method for faults of circuit patterns on MCM(Multichip Module) or PCB(Printed Circuit Board) substrates with electron beams of a SEM(Scanning Electron Microscope) by inducing voltage contrast on the signal line. The experimentation employes dual potential electron beams for the fault characterization of circuit patterns with a commercial SEM without modifying its structure. The testing procedure utilizes only one electron gun for the generation of dual potential electron beams by two different accelerating voltages, one for charging electron beam which introduces the yield of secondary electron $\delta$ < 1 and the other for reading beam which introduces $\delta$ > 1. Reading beam can read open's/short's of a specific net among many test nets, simultaneously discharging during the reading process for the next step, by removing its voltage contrast. The experimental results of testing the copper signal lines on glass-epoxy substrates showed that the state of open's/short's had generated the brightness contrast due to the voltage contrast on the surface of copper conductor line, when the net had charged with charging electron beams of 7KV accelerating voltages and then read with scanning reading electron beams of 2KV accelerating voltages in 10 seconds. The experimental results with Au pads of a IC die and Au plated Cu pads of BGA substrates provided the simple test method of circuit lines with 7KV charging electron beam and 2KV reading beam. Thus the characterization method showed that we can test open and short circuits of the net nondestructively by using dual potential electron beams with one SEM gun.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.901-904
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• 2005

Testing of mixed-signal circuit has become a difficult task for test engineers and efficient test solution to these problems are needed. In this paper a new specification-based mixed-signal test method called TSS(Time Slot Specification) using high performance current sensors and a novel test point selection technique without heavy computational overhead are proposed. External output and power nodes are used for test points and accessed by the current sensors in the ATE.