• The Transactions of The Korean Institute of Electrical Engineers
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• v.61 no.3
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• pp.373-379
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• 2012

This paper presents a fault location algorithm based on the adaptively estimated value of the local sequence source impedance for faults on a parallel transmission line. This algorithm uses only the local voltage and current signals of a faulted circuit. The remote current signals and the zero-sequence current of the healthy adjacent circuit are calculated by using the current distribution factors together with the local terminal currents of the faulted circuit. The current distribution factors consist of local equivalent source impedance and the others such as fault distance, line impedance and remote equivalent source impedance. It means that the values of the current distribution factors can change according to the operation condition of a power system. Consequently, the accuracy of the fault location algorithm is affected by the two values of equivalent source impedances, one is local source impedance and the other is remote source impedance. Nevertheless, only the local equivalent impedance can be estimated in this paper. A series of test results using EMTP simulation data show the effectiveness of the proposed algorithm. The proposed algorithm is valid for a double-circuit transmission line system where the equivalent source impedance changes continuously.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.3
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• pp.85-97
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• 2002

STUMPS has been widely used for built-in self-test of scan design with multiple scan chains. In the STUMPS architecture, there is very high correlation between the bit sequences in the adjacent scan chains. This correlation causes circuits lower the fault coverage. In order to solve this problem, an extra combinational circuit block(phase shifter) is placed between the LFSR and the inputs of STUMPS architecture despite the hardware overhead increase. This paper introduces an efficient test pattern generation technique and built-in self-test architecture for sequential circuits with multiple scan chains. The proposed test pattern generator is not used the input of LFSR and phase shifter, hence hardware overhead can be reduced and sufficiently high fault coverage is obtained. Only several XOR gates in each scan chain are required to modify the circuit for the scan BIST, so that the design is very simple.

• Progress in Superconductivity
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• v.6 no.1
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• pp.7-12
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• 2004

Due to the very fast switching speed of Josephson junctions, superconductive digital circuit has been a very good candidate fur future electronic devices. High-speed and Low-power microprocessor can be developed with Josephson junctions. As a part of an effort to develop superconductive microprocessor, we have designed an RSFQ 4-bit ALU (Arithmetic Logic Unit) in a pipelined structure. To make the circuit work faster, we used a forward clocking scheme. This required a careful design of timing between clock and data pulses in ALU. The RSFQ 1-bit block of ALU used in this work consisted of three DC current driven SFQ switches and a half-adder. We successfully tested the half adder cell at clock frequency up to 20 GHz. The switches were commutating output ports of the half adder to produce AND, OR, XOR, or ADD functions. For a high-speed test, we attached switches at the input ports to control the high-speed input data by low-frequency pattern generators. The output in this measurement was an eye-diagram. Using this setup, 1-bit block of ALU was successfully tested up to 40 GHz. An RSFQ 4-bit ALU was fabricated and tested. The circuit worked at 5 GHz. The circuit size of the 4-bit ALU was 3 mm ${\times}$ 1.5 mm, fitting in a 5 mm ${\times}$ 5 mm chip.

• Journal of Power Electronics
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• v.16 no.6
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• pp.2202-2211
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• 2016

In certain applications, such as IPT-based EV charger (IPTEC), any variation in alignment and distance between pickup and charger primary leads to a change in leakage and magnetic impedance magnitudes. The power transmission capacity is not always at the maximum level because of these variations. This study proposes a new low-cost tracking method that achieves the Maximum Inductive Power Transmission Capacity (MIPTC). Furthermore, in the proposed method, the exchange of information between load and source is not required. For an application such as IPTEC, the load detected by the IPTEC varies continuously with time because of the change in state of the charge. This load variation causes a significant variation in IPT resonant circuit voltage gain. However, the optimized charging output voltage should be kept constant. From the analysis of the behavior of the IPT circuit at different working frequencies and load conditions, a MIPTC operation point that is independent of load condition can be identified. Finally, the experimental results of a developed prototype IPT circuit test show the performance of the proposed method.

• Journal of Welding and Joining
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• v.33 no.3
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• pp.47-53
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• 2015

By the trends of electronic package to be more integrative, the fine Cu trace pitch of organic PCB is required to be a robust design. In this study, the short circuit failure mechanism of PCB with a Cl element under the Temperature humidity bias test ($85^{\circ}C$/85%RH/3.5V) was examined by micro-structural study. A focused ion beam (FIB) and an electron probe micro analysis (EPMA) were used to polish the cross sections to reveal details of the microstructure of the failure mode. It is found that $CuCl_x$ were formed and grown on Cu trace during the $170^{\circ}C$/3hrs and that $CuCl_x$ was decomposed into Cu dendrite and $Cl_2$ gas during the $85^{\circ}C$/85%RH/3.5V. It is suggested that Cu dendrites formed on Cu trace lead to a short circuit failure between a pair of Cu traces.

• Journal of Biomedical Engineering Research
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• v.32 no.1
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• pp.32-36
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• 2011

The insufflators in endoscopic surgery supply carbon dioxide to make the air-filled cavity in the abdomen. It contains many kinds of pneumatic and electronic parts and they are connected with the air tubes and electrical wires. The printed circuit boards (PCB) perform wiring, holding and cooling tasks in electronic systems. In this study, the PCB is used as the air channel for insufflators to decrease the cost, volume, and the malfunction according to aging of the device. Three layers of PCB made of FR4 are combined with prepreg as adhesive which has the internal airway channel according to the design. By mounting the pressure sensors and valves, the PCB based fluidic system is implemented. After calibration of flow sensor, the flow rate of the gas also can be measured. The climate test, temperature test, and biocompatibility test showed this idea can be used in insufflators for laparoscopic surgery.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.1
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• pp.71-78
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• 2013

In highly reliable and durable systems, failures due to aging might result in catastrophes. Aging monitoring techniques to prevent catastrophes by predicting such a failure are required. Aging can be monitored by performing a delay test at faster clocks than functional clock in field and checking the current delay state from the test clock frequencies at which the delay test is passed or failed. In this paper, we focus on test clock control scheme for a system-on-chip (SoC) with multiple clock domains. We describe limitations of existing at-speed test clock control methods and present an on-chip faster-than-at-speed test clock control scheme for intra/inter-clock domain test. Experimental results show our simulation results and area analysis. With a simple control scheme, with low area overhead, and without any modification of scan architecture, the proposed method enables faster-than-at-speed test of SoCs with multiple clock domains.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.67 no.4
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• pp.595-599
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• 2018

Interruption system with the transformer type superconducting fault current limiter(TSFCL) is proposed in this paper. The interruption system with a TSFCL is a technology that it maximizes the interruption function of a mechanical DC circuit breaker using a transformer and a superconducting fault current limiter. By a TSFCL, the system limits the fault current till the breakable current range in the fault state. Therefore, the fault current could be cut off by a mechanical DC circuit breaker. The Interruption system with a TSFCL were designed using PSCAD/EMTDC. In addition, the Interruption system with a TSFCL was applied to the DC test circuit to analyze characteristics of a current-limiting and a interruption operation. The simulation results showed that the Interruption system with a TSFCL interrupted the fault current in a stable when a fault occurred. Also, The current-limiting rate of the Interruption system with a TSFCL was approximately 69.55%, and the interruption time was less than 8 ms.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.16 no.6
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• pp.137-144
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• 2002

Low voltage circuit breakers which interrupt rapidly and raise the reliability of power supply are widely used in power distribution systems. In the paper, it has been investigated how much interrupting capability is improved by correcting the shape of the contact system in molded case circuit breaker(below MCCB), especially arc runner. Prior to the interrupting testing, it is necessary for the optimum design to analyze electromagnetic forces on the contact system generated by current and flux density. This paper presents both our computational analysis and test results on contact system in MCCB.

• Journal of IKEEE
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• v.13 no.1
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• pp.19-29
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• 2009

For two input ESD protection schemes utilizing the NMOS protection device or the lvtr_thyristor protection device, which is suitable for high-frequency CMOS ICs, we attempt an in-depth comparison study on the HBM ESD protection level in terms of lattice heating inside the protection devices and the peak voltage applied to the gate oxides in the input buffer through DC, mixed-mode transient, and AC analyses utilizing the 2-dimensional device simulator. For this purpose, we suggest a method for the equivalent circuit modeling of the input HBM test environment for the CMOS chip equipped with the input ESD protection circuit. And by executing mixed-mode simulations including up to four protection devices and analyzing the results for five different test modes, we attempt a detailed analysis on the problems which can be occurred in a real HBM test. In this procedure, we explain about the strength and weakness of the two protection schemes as an input protection circuit for high-frequency ICs, and suggest guidelines relating to the design of the protection devices.