• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.12
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• pp.198-208
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• 1995

BiCMOS circuit consist of CMOS part which constructs logic function, and bipolar part which drives output load. Test to detect stuck-open faults in BiCMOS circuit is important, since these faults do sequential behavior and are represented as transition faults. In this paper, proposes a method for efficiently detecting transistor stuck-open faults in BiCMOS circuit by transforming them into slow-to=rise transition and slow-to-fall transition. In proposed method, BiCMOS circuit is transformed into equivalent gate-level circuit by dividing it into pull-up part which make output 1, and pull-down part which make output 0. Stuck-open faults in transistor are modelled as transition fault in input line of gate level circuit which is transformed from given circuit. Faults are detceted by using pull-up part gate level circuit when expected value is '01', or using pull-down part gate level circuit when expected value is '10'. By this method, transistor stuck-open faults in BiCMOS circuit are easily detected using conventional gate level test generation algorithm for transition fault.

• Proceedings of the KIEE Conference
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• 2005.07a
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• pp.569-571
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• 2005

In case of dead-tank circuit breaker with the earthed enclosure, the dielectric performance for phase to ground should be verified under the hot-gas condition produced by the current interruption. This test condition is required in breaking test duties with the rated short-circuit current and rated voltage. And, KERI has completed the reinforcement of the synthetic testing facilities and these facilities have the testing capacity which enables the full-pole testing for 800kV circuit breaker by adopting the series voltage injection method. So, this paper introduced the test circuit and procedures about the full-pole and the multi-part testing method which was devised to estimate the full -insulation of phase-to-ground for the multi-pole and dead-tank circuit breaker.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.9
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• pp.53-60
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• 1997

In this paper, an efficient BILBO(named EBILBO) is proposed for batch testing application when a BIST (built-in self test) circuit is implemented on ASIC. In a large and complex circuit, the proposed algorithm of batch testing has one pin-count that can easily control 4 test modes in the normal speed of circuit operation. For the implementation of the BIST cifcuit, the test patern needed is generated by PRTPG(pseudo-random test pattern generator) and the ouput is observed by proposed algorithm is easily modified, such as the modelling of test pattern genration, signature EBILBO area and performance of the implemented BIST are evaluated using ISCAS89 benchmark circuits. As a resutl, in a circuit above 600 gates, it is confirmed that test patterns are genrated flexibly about 500K as EBILBO area is 59%, and the range of fault coverage is from 88.3% to 100%. And the optimized operation frequency of EBILBO designed and the area are 50MHz and 150K respectively. On the BIST circit of the proposed batch testing, the test mode of EBILBO is able to execute as realtime that has te number of s$\^$+/n$\^$+/(2s/2p-1) clocks simultaneously with the normal mode of circuit operation. Also the proposed algorithm is made of the library with VHDL coding thus, it will be widely applied to DFT (design for testability) that satisfies the design and test field.

• Proceedings of the KSR Conference
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• 2007.05a
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• pp.1701-1706
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• 2007

Jointless AF(Audio Frequency) Track Circuit is more comfortable than exist joint track circuit. This electrical circuit's function is detection train on rail, and transmit information between wayside and vehicle. 'Korea Railroad Corporation' proposed for revision of the Korean railway standards(KRS SG 0038-06 R, 2006.5.16) "Non-insulated AF Track Circuit". This proposal equipment developed to extend use for station of National Railway exist line. According to test standards Korean railway safety law and its ordinances, which were committed to Korea Railroad Research Institute, the professional committee 'Railway facility sector II' have helded on January in 2007. In this investigation, the changed test norm will be review the difference of important function test standards of new version to conform effectivity and safety test procedure according to the KS A 1025.

• ETRI Journal
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• v.28 no.3
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• pp.355-363
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• 2006

This paper presents a low-cost RF parameter estimation technique using a new RF built-in self-test (BIST) circuit and efficient DC measurement for 4.5 to 5.5 GHz low noise amplifiers (LNAs). The BIST circuit measures gain, noise figure, input impedance, and input return loss for an LNA. The BIST circuit is designed using $0.18\;{\mu}m$ SiGe technology. The test technique utilizes input impedance matching and output DC voltage measurements. The technique is simple and inexpensive.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.125-128
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• 2001

In this paper, we propose a low power Scan-based Built-ln Self Test based on circuit partitioning and pattern suppression using modified test control unit. To partition a CUT(Circuit Under Testing), the MHPA(Multilevel Hypergraph Partition Algorithm) is used. As a result of circuit partition, we can reduce the total length of test pattern, so that power consumptions are decreased in test mode. Also, proposed Scan-based BIST architecture suppresses a redundant test pattern by inserting an additional decoder in BIST control unit. A decoder detects test pattern with high fault coverage, and applies it to partitioned circuits. Experimental result on the ISCAS benchmark circuits shows the efficiency of proposed low power BIST architecture.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.6
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• pp.48-55
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• 1998

In this work, the testable CAM(Content Addressable Memory) is designed to perform the test effectively by inserting the ECC(Error Checking Circuit) inside the CAM. The designed CAM has the circuit which is capable of testing the functional faults in read, write, and match operations. In general the test circuit inserted causes the increase of total circuit area, Thus this work, utilizes the new MTA code to reduce the overhead of an area of the built-in test circuit which has a conventional parallel comparator. The designed circuit was verified using the VHDL simulator and the layout was performed using the 0.8${\mu}{\textrm}{m}$ double metal CMOS process. About 30% reduction of a circuit area wad achieved in the proposed CAM using the XOR circuit

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.49 no.6
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• pp.322-329
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• 2000

BIST(Built-in Self Test) has been considered as the most promising DFT(design-for-test) scheme for the present and future test strategy. The most serious problem in applying BIST(Built-in Self Test) into a large circuit is the excessive increase in test time. This paper is focused on this problem. We proposed a new BIST construction scheme which uses a parallel divide-and-conquer method. The circuit division is performed with respect to some internal nodes called test points. The test points are selected by considering the nodal connectivity of the circuit rather than the testability of each node. The test patterns are generated by only one linear feedback shift register(LFSR) and they are shared by all the divided circuits. Thus, the test for each divided circuit is performed in parallel. Test responses are collected from the test point as well as the primary outputs. Even though the divide-and-conquer scheme is used and test patterns are generated in one LFSR, the proposed scheme does not lose its pseudo-exhaustive property. We proposed a selection procedure to find the test points and it was implemented with C/C++ language. Several example circuits were applied to this procedure and the results showed that test time was reduced upto 1/2151 but the increase in the hardware overhead or the delay increase was not much high. Because the proposed scheme showed a tendency that the increasing rates in hardware overhead and delay overhead were less than that in test time reduction as the size of circuit increases, it is expected to be used efficiently for large circuits as VLSI and ULSI.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.8
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• pp.49-63
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• 1997

This paper presents a current sensor that detects defects in CMOS integrated circuits using the current testing technique. The current sensor is built in a CMOS integrated circuit to test an abnormal current. The proposed circuit has a very small impact on the performance of the circuit under test during the normal mode. In the testing mode, the proposed circuit detects the abnormal current caused by permanent manufacturing defects and determines whether the circuit under test is defect-free or not. The proposed current sensor is simple and requires no external voltage and current sources. Hence, the circuit has less area and performance degradation, and is more efficient than any previous works. The validity and effectiveness are verified through the HSPICE simulation on circuits with defects.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.5
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• pp.1089-1095
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• 2005

This paper presents a new low-cost Built-In Self-Test (BIST) circuit for 50Hz low noise amplifier (LNA). The BIST circuit is designed for system-on-chip (SoC) transceiver environment. The proposed BIST circuit measures the LNA specifications such as input impedance, voltage gaih, noise figure, and input return loss all in a single SoC environment.