• Journal of Electrical Engineering and Technology
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• v.8 no.3
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• pp.603-609
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• 2013

In this paper, we describe the analysis of inkjet-printed silver (Ag) patterns on epoxy-coated substrates according to several reliability evaluation test method guidelines for conventional printed circuit boards (PCB). To prepare patterns for the reliability analysis, various regular test patterns were created by Ag inkjet printing on flame retardant 4 (FR4) and polyimide (PI) substrates coated with epoxy for each test method. We coated the substrates with an epoxy primer layer to control the surface energy during printing of the patterns. The contact angle of the ink to the coated epoxy primer was $69^{\circ}$, and its surface energy was 18.6 $mJ/m^2$. Also, the substrate temperature was set at $70^{\circ}C$. We were able to obtain continuous line patterns by inkjet printing with a droplet spacing of $60{\mu}m$. The reliability evaluation tests included the dielectric withstanding voltage, adhesive strength, thermal shock, pressure cooker, bending, uniformity of line-width and spacing, and high-frequency transmission loss tests.

• Progress in Superconductivity
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• v.11 no.1
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• pp.19-24
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• 2009

Among the various types of fault current limiters, superconducting fault current limiters could be the most preferable choice for high voltage electric power systems owing to the remarkable current limiting characteristics of superconductors. But, there have been no commercial superconducting fault current limiters which were installed into actual electric power systems until these days due to some remained technical and economical problems. Thus, in order to promote the development and application of the superconducting fault current limiters into real field, it is essential to understand the power utilities’ requirements for their networks and also suitable test method and some specifications should be prepared. This paper focuses on the matters of test requirements and standardization issues that should be prepared for commercialization of superconducting fault current limiters. The unique current limiting characteristics of superconducting fault current limiters were investigated and related other standards including circuit breakers, transformers, reactors, power fuse, and fused circuit breakers were compared to setup the basis of novel specification of superconducting fault current limiters. Furthermore, required essential test procedures for superconducting fault current limiters were suggested.

• Proceedings of the KIEE Conference
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• 2001.07a
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• pp.38-40
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• 2001

Measuring technology based on the computer and software is used worldwideiy by the aids of remarkably improved digital technology and measuring devices, and the electro- magnetic interference due to high currents and high voltages is being solved by the helps of applied optic instrumentation technology. The automatic acquisition, analysis and storage system of test data is available for utilizing the numerical computation technology. The measuring accuracy and testing efficiency are thus much higher because of the developed technologies. In this paper, the construction of data acquisition system in KERI including measuring devices and its application to the short circuit test are described, and additionally the algorithm of the analyzing program for the automatic process of test data and the results of analyses are described.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.9
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• pp.1442-1447
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• 1990

In this paper we propose the search algorithm of the boundary nodes that defined as the circuit segmentation when CUT is tested by pseudo-exhaustive testing. The algorithm treats the testability values of the nodes in CUT as the population composed of teh raw data, and after examines the level of significance a and then estimate the confidence interval of teh testability values. Thus One can easily searched the c9oundary nodes and PO of sub circuits. The proposed algorithm has been implemented under UNIX OS with C-language, applied to the combinational logic CUT. As a result, it is shown that the pseudo-exhaustive test patterns are least generated when \ulcornerhas 0.786. We confirmed that the rate of test pattern is 1.22%, compared with exhaustive test.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.8
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• pp.1-9
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• 1998

A new parallel test algorithm and a built-in self test (BIST) architecture are developed to test various types of functional faults efficiently in content addressable memories (CAMs). In test mode, the read oepratin is replaced by one parallel content addressable search operation and the writing operating is performed parallely with small peripheral circuit modificatins. The results whow that an efficient and practical testing with very low complexity and area overhead can be achieved.

• Journal of Radiation Protection and Research
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• v.25 no.4
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• pp.197-205
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• 2000

A prototype electronic dosimeter(PED) adopting a silicon PIN diode detector as a radiation detector has been developed, manufactured and test-evaluated. A radiation signal processing circuit has been electronically tested and then the radiation detection characteristics of this PED has been performance-tested by using a reference photon radiation field. As a result in a electronic performance test, radiation signals from a detector were well observed in the signal processing circuit. The radiation detection sensitivity of this PED after several test-irradiations to $^{137}Cs$ gamma radiation source appeared to be 1.85 cps/$Gy{\cdot}h^{-1}$ with 19.3% of the coefficient of variation, which satisfied the performance criteria for the active personnel radiation monitor. Further improvement of the electronic circuit and operating program will enable the PED to be used in personal monitoring purpose.

• Journal of Digital Contents Society
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• v.18 no.3
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• pp.607-612
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• 2017

The use of RaspberryPi in building an embedded system may be difficult for users in understanding the circuit and the hardware cost. This paper proposes a solution that can test the systems virtually. The solution consists of three elements; (i) editor, (ii) interpreter and (iii) simulator and provides nine full modules and also allows the users to configure/run/test their own circuits like real environment. The task of abstraction for modules through the actual circuit test was carried out on the basis of the data sheet and the specification provided by the manufacturer. If we can improve the level of quality of our solution, it can be useful in terms of cost reduction and easy learning. To achieve this end, the electrical physics engine, the level of interpreter that can be ported to the actual board, and a generalization of the simulation logic are required.

• Transactions of the Korean Society for Noise and Vibration Engineering
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• v.13 no.4
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• pp.300-307
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• 2003

This paper presents the multi-mode noise reduction of smart panels of which passive piezoelectric shunt damping is introduced. For the piezoelectric shunt damping, a passive shunt circuit composed of inductors and a load resistor is connected to the piezoelectric patch mounted on the panel structure. An electrical impedance model is introduced for the system based on the measured electrical impedance, and the criteria for maximum energy dissipation at the shunt circuit is used to find the optimal shunt parameters. For multi-mode shunt damping, the shunt circuit is modified by the introduction of a block circuit. Also the optimal location of the piezoelectric patch is studied by finite element analysis in order to cause the maximum admittance from the patch for each mode of the structure. An acoustic test is performed for the panels and a remarkable noise reduction is obtained in multiple modes of the panel structure.

• Journal of Electrical Engineering and Technology
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• v.2 no.4
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• pp.434-440
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• 2007

This paper proposes a fault location algorithm for double-circuit transmission lines in the case of single line-to-ground fault. The proposed algorithm requires the voltage and current from the sending end of the transmission line. The fault distance is simply determined by solving a second order polynomial equation which is achieved directly by the analysis of the circuit. In order to testify the performance of the proposed algorithm, several other conventional approaches have been taken out to compare with it. The test results corroborate its superior effectiveness.

• 제어로봇시스템학회:학술대회논문집
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• 1999.10a
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• pp.281-283
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• 1999

This topic presents an inductor short turn testing. From the rudimentary principles, the quality factor(Q) decreases due to inductor short turn. Frequency response varies because of the variation of circuit inductance and resistance. In general, short turn circuit testing is performed by comparing the ratio of an inductance and resistance of inductor in that particular circuit. An alternative method can be done by considering the response of second order circuit which can give both dynamic and static testing, whereas static testing give an error results not more than 2 turns. For dynamic testing, the result is more accurate, which can test fur the short turn number form 1 turn onward.