• Title/Summary/Keyword: in-circuit test

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Hysteresis Modeling of the Sealed Flooded Lead Acid Battery for SOC Estimation (SOC 추정을 위한 밀폐형 Flooded 연축전지의 히스테리시스 모델링)

  • Khan, Abdul Basit;Choi, Woojin
    • Proceedings of the KIPE Conference
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    • 2016.07a
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    • pp.309-310
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    • 2016
  • Sealed flooded lead acid batteries are becoming popular in the industry because of their low cost as compared to their counterparts. State of Charge (SOC) estimation has always been an important factor in battery management systems. For the accurate SOC estimation, open circuit voltage (OCV) hysteresis should be modelled accurately. The hysteresis phenomenon of the sealed flooded lead acid battery is discussed in detail and its ultimate modeling is proposed based on the conventional parallelogram method. The SOC estimation is performed by using Unscented Kalman Filter (UKF) while the parameters of the battery are estimated using Auto Regressive with external input (ARX) method. The validity of the proposed method is verified by the experimental results. The SOC estimation error by the proposed method is less than 3 % all wing the 125hr test.

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Power-Gating Structure with Virtual Power-Rail Monitoring Mechanism

  • Lee, Hyoung-Wook;Lee, Hyun-Joong;Woo, Jong-Kwan;Shin, Woo-Yeol;Kim, Su-Hwan
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.8 no.2
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    • pp.134-138
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    • 2008
  • We present a power gating turn-on mechanism that digitally suppresses ground-bounce noise in ultra-deep submicron technology. Initially, a portion of the sleep transistors are switched on in a pseudo-random manner and then they are all turned on fully when VVDD is above a certain reference voltage. Experimental results from a realistic test circuit designed in 65nm bulk CMOS technology show the potential of our approach.

The design of on-board inverter using IGBT (IGBT를 이용한 탑재형 인버터 설계)

  • Kim, In-Soo;Kim, Seong-Shin;Lee, Kyung-Seok;Hwang, Yong-Ha
    • Proceedings of the KIEE Conference
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    • 1992.07b
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    • pp.1126-1128
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    • 1992
  • The object of this study is the design of 3 phase on-board inverter. The key point in the inverter design is the selection of switching device, and its performance effects that of total system. In this study, six-step square wave inverter was designed using IGBT ( Insulated Gate Bipolar Transistor ) which has the advantages of MOSFET and bipolar transistor as switching device. The condition of being small and light which is the one of requirements for on-board equipment was accomplished by using IGBT module and optimising the snubber circuit, and the reliablity was increased. It is confirmed that the designed inverter satisfies the required performance through the performance and environment test.

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Characteristic Analysis according to Switching Method in SRM (상권선 스위칭방식에 따른 SRM의 특성해석)

  • Kim Tae-Hyoung;Ahn Jin-Woo;An Young-Ju
    • Proceedings of the KIPE Conference
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    • 2004.07a
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    • pp.46-49
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    • 2004
  • Switched Reluctance Motor(SRM) has been researched for its superior characteristics. The SRM drive system has simple mechanical and magnetic structure, and it requires simple power electronic drive circuit. It is to be compatible to wide range adjustable speed drive system because it has the same driving characteristics of DC series motor's, easy control principle and high efficiency characteristics. In this paper, 2 types of excitation strategy are researched. Conventional 1-phase excitation and 2-phase excitation method are compared and tested. Though 1-phase excitation method is robust and has high performance, 2-phase excitation method has some merit in appling power device. Some simulation and test results are foaled with some analysis.

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A Study on the Improvement of the Electrical Stability Versus MgO Addictive for ZnO Ceramic Varistors (MgO 첨가에 따른 ZnO 세라믹 바리스터의 신뢰성 향상에 관한 연구)

  • 소순진;김영진;송민종;박복기;박춘배
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2001.07a
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    • pp.427-430
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    • 2001
  • The degradation characteristics versus MgO Additive for the ZnO ceramic devices fabricated by the standard ceramic techniques is investigated in this study. It were made these devices be basic Matsuoka's composition. Especially, MgO were added to analyze the degradation characteristics and sintered in air at 1300$^{\circ}C$. The conditions of DC degradation test were 115${\pm}$2$^{\circ}C$ for 12h. Using XRD and SEM, the phase and microstructure of samples were analyzed respectively. The elemental analysis in the microstructures was used by EDS, E-J analysis was used to determine ${\alpha}$ . Frequency analysis was accomplished to understand the relationship between R$\sub$g/ and $R_{b}$ with the electric stress at the equivalent circuit.

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Characteristics of polymer arrester with pressure relief structure (폴리머 피뢰기의 방압구조 및 특성)

  • Han, Dong-Hee;Cho, Han-Goo;Han, Se-Won
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2004.07b
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    • pp.1109-1112
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    • 2004
  • This study reports on the pressure relief design and braided composite of surge arrester. Surge arresters with porcelain housing must not have explosive breakage of the housing to minimize damage to other equipment when subjected to internal high short circuit current. As a solution, this study describes pressure relief design performance of arresters with braided composite module. In general, braided composite has Potential for improved impact and delamination resistance. Manufacturing processes of the braided composite could also be automated and could potentially lead to lower costs. Therefore, in consideration of characteristics of pressure relief for polymer arrester, the fabric pattern of braided composite was decided. And Polymer arrester module was manufactured with braid. The mechanisms of pressure occurrence and relief were investigated basically by analyzing arc energy and the correlation between thermal shock and indoor pressure in pressure relief test.

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The Design of Path Length Controller in Ring Laser Gyroscope for Attitude Control in the LEO satellite (위성 자세제어 자이로 센서 피에조 구동기 설계)

  • Kim, Eui-Chan
    • Proceedings of the IEEK Conference
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    • 2009.05a
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    • pp.341-343
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    • 2009
  • The Ring Laser Gyroscope makes use of the Sagnac effect within a resonant ring cavity of a He-Ne laser and has more accuracy than the other gyros. The Low Earth Orbit satellite for observatory use require the high accuracy Gyro to control and determine the altitude because of the need of payload pointing accuracy. In this paper, The theory of the Path Length Control is explained. The electrical design of Path Length Controller Is described. The Design for Path Length Controller is composed of the demodulator, integrator, phase shifter, high voltage amplifier. We apply the circuit to 28cm square ring laser gyro and get the test results.

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An Accurate and Matching-Free MOSFET's Threshold Voltage Extraction Using New Novel Circuit Thencique (새로운 회로기술을 이용한 고정밀 Matching-Free MOSFET 문턱전압 추출)

  • 유종근;신남승;박종태
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.32A no.1
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    • pp.166-178
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    • 1995
  • An accurate threshold voltage extraction scheme for MOS transistors is presented. In contrast to alternative methods recently reported in the literature, this scheme does not need matched replica of the transistor under test, and thus can be applied more effectively and accurately to raal-time on-chip applications where threshold voltage measurements are required for many transistors with various geometries and bias conditions. The proposed scheme is accurately implemented in a matching-free way using a ratio-indepentent switched-capacitor subtracting amplifier and a dynamic current mirror. Nonideal effects associated with these circuits have been investiggated and compensated.

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Compression of Simulation Results by Sampling (샘플링에 의한 시뮬레이션 결과의 압축)

  • 안태균;최기영
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.31A no.5
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    • pp.158-169
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    • 1994
  • It is very common in today 's design practice to simulate a big design with a large set of test vectors thereby generating a huge set of data (simulation results) to be analyzed. As the design grows, the simulation results grow and become harder to handled. In this paper, we present algorithms for the compression and regeneration of simulation results. The compression is performed by sampling nets in a circuit. If the user wants to examine the lost part of the data, it is quickly regenerated by applying incremental simulation technique. Experimental results obtained for several practical circuits show that the compression ratio of 10 is easily obtained while maintaining a reasonably fast regeneration of data on a 15.7 MIPS workstation. Using the proposed method we can effectively reduce debug cycle time.

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Circuit Techniques for Low-Power Data Drivers of TFT-LCDs

  • Choi, Byong-Deok;Kwon, Oh-Kyong
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.1 no.3
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    • pp.167-181
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    • 2001
  • A stepwise driving method was used for reducing the AC power consumption in a TFT-LCD. The AC power takes the largest portion of the total power consumption of a TFT-LCD. Experimental results confirmed that the AC power saving efficiency reached up to 75% when a 5-stepwise driving with each step time of $2\mu$ sec was applied to a 14.1 inch-diagonal XGA TFT-LCD. The second largest component of power consumption called the DC power comes from the quiescent currents in Op-amps. A simple and efficient architecture was proposed in this work to reduce this DC power consumption: Half of the Op-amps have the 5V-supplies, and the rest half have the 10V-supplies, and two Op-amps are shared by adjacent two channels. Measurements of test circuits showed that this simple method could reduce over 40% of the DC power consumption..

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