• Journal of Biomedical Engineering Research
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• v.26 no.4
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• pp.199-205
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• 2005

When recording single-unit responses from neural systems, a common problem is the accurate detection of spikes (action potentials) in the presence of competing unwanted (noise) signals. While some sources of noise can be readily dealt with through filtering or 'template subtraction' techniques, other sources present a more difficult problem. In particular, noise components introduced by power supplies, which contain harmonics of the power-line frequency, can be particularly troublesome in that they can mimic the shape of the desired spikes. Thus, standard 'template subtraction' techniques or notch-filtering approaches are not appropriate. In this study, we propose the use of a novel template-subtraction scheme that involves estimating the power-line noise waveform and using cross-correlation techniques to subtract them from the recordings. This technique requires two key steps: (1) cross-correlation analysis of each recorded waveform extracts a robust representation of the power-line noise waveform and (2) a second level of cross-correlation to successfully subtract that representation from each recorded waveform. This paper describes this algorithm and provides examples of its implementation using actual recorded waveforms that are contaminated with these noise signals. An improvement (reduction) in the noise level is reported, as are suggestions for future implementation of this strategy.

• Journal of Satellite, Information and Communications
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• v.11 no.2
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• pp.14-17
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• 2016

This paper describes the implementation of automatic number-braille converter based on image processing for the blind people. The algorithm is consists of four main steps. First step is binary image conversion of the input image obtained by the camera. the second step is segmentation operation by means of dilation and labelling of the character. Next step is calculation of cross-correlation between segmented text image and pre-defined text-pattern image. The final step is generation of brail output which is relevant to input image. The computer simulation result was showing 91.8% correct conversion rate for arabian numbers which is printed in A4-sheet and practical possibility was also confirmed by using implemented automatic number-braille converter based on DSP image processing board.

• Fibers and Polymers
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• v.7 no.3
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• pp.276-285
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• 2006

Development and numerical implementation for an elastoplastic constitutive model for anisotropic and asymmetric materials are presented in this paper. The Coulomb-Mohr yield criterion was modified to consider both the anisotropic and asymmetric properties. The modified yield criterion is an isotropic function of the principal values of a symmetric matrix which is linearly transformed from the Cauchy stress space. In addition to the constitutive equation, the numerical treatment for the singularity in the vertex region of yield surface and stress integration algorithm based on elastoplasticity were presented. In order to assess the accuracy of numerical algorithm, isoerror maps were considered. Also, extension of a strip with a circular hole was simulated and results compared with those obtained using the (smooth) Mises yield criterion to validate stress output for a complex stress state.

• Journal of the Optical Society of Korea
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• v.19 no.6
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• pp.592-603
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• 2015

In this paper, an optical implementation of a novel asymmetrical cryptosystem combined with D-H secret key sharing and triple DES is proposed. The proposed optical cryptosystem is realized by performing free-space interconnected optical logic operations such as AND, OR and XOR which are implemented in Mach-Zehnder type interferometer architecture. The advantage of the proposed optical architecture provides dual outputs simultaneously, and the encryption optical setup can be used as decryption optical setup only by changing the inputs of SLMs. The proposed cryptosystem can provide higher security strength than the conventional electronic algorithm, because the proposed method uses 2-D array data, which can increase the key length surprisingly and uses 3DES algorithm, which protects against “meet in the middle” attacks. Another advantage of the proposed asymmetrical cryptosystem is that it is free to change the user’s two private random numbers in generating the public keys at any time. Numerical simulation and performance analysis verify that the proposed asymmetric cryptosystem is effective and robust against attacks for the asymmetrical cipher system.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.67 no.1
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• pp.9-14
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• 2018

In this paper, we introduce an AES-based security chip for the embedded system of Internet of Things(IoT). We used Verilog HDL to implement the AES algorithm in FPGA. The designed AES module creates 128-bit cipher by encrypting 128-bit plain text and vice versa. RTL simulations are performed to verify the AES function and the theory is compared to the results. An FPGA emulation was also performed with 40 types of test sequences using two Altera DE0-Nano-SoC boards. To evaluate the performance of security algorithms, we compared them with AES implemented by software. The processing cycle per data unit of hardware implementation is 3.9 to 7.7 times faster than software implementation. However, there is a possibility that the processing speed grow slower due to the feature of the hardware design. This can be solved by using a pipelined scheme that divides the propagation delay time or by using an ASIC design method. In addition to the AES algorithm designed in this paper, various algorithms such as IPSec can be implemented in hardware. If hardware IP design is set in advance, future IoT applications will be able to improve security strength without time difficulties.

• Journal of Korea Society of Industrial Information Systems
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• v.10 no.1
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• pp.49-57
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• 2005

ATM Form has defined the guaranteed frame rate (GFR) service to provide minimum cell rate (MCR) guarantees for TCP traffic in ATM networks and allow it to fairly share residual bandwidth. GFR switch implementation consists of the frame-based generic cell rate algorithm (F-GCRA) and a frame forwarding mechanism. The F-GCRA identifies frames that are eligible for an MCR guarantee. The frame forwarding mechanism buffers cells at a frame unit according to information provided by the F-GCRA and forwards the buffered cells to an output port according to its scheduling discipline. A simple GFR mechanism with shared buffer with a global threshold is a feasible implementation mechanism, but has been known that it is insufficient to guarantee the MCR. This paper has estimated performance of GFR service for TCP traffic over ATM switches with the simple FIFO-based mechanism

• Journal of Institute of Control, Robotics and Systems
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• v.18 no.9
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• pp.878-886
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• 2012

This paper investigates the implementation and flight test of realtime vision guided autopilot system based on virtual instrumentation platform. A graphical design process via virtual instrumentation platform is fully used for the image processing, communication between systems, vehicle dynamics control, and vision coupled guidance algorithms. A significatnt ojective of the algorithm is to achieve an environment robust autopilot despite wind and an irregular image acquisition condition. For a robust vision guided path tracking and hovering performance, the flight path guidance logic is combined in a multi conditional basis with the position estimation algorithm coupled with the vehicle attitude dynamics. An onboard flight test equipped with the developed realtime vision guided autopilot system is done using the rotary UAV system with full attitude control capability. Outdoor flight test demonstrated that the designed vision guided autopilot system succeeded in UAV's hovering on top of ground target within about several meters under geenral windy environment.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.42 no.5 s.305
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• pp.157-164
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• 2005

The conventional adaptive detectors can not maintain sufficient detection performance at the presence of non-stationary clutter with unknown characteristics. This is caused by the lack of a priori information about clutter parameters changing over radar coordinates. To solve this problem, it is necessary to use clutter classifiers which have functions, such as the selection of the applied algorithm and its parameters extraction according to clutter conditions. In this paper, we describe the implementation of a clutter environment classifier for adaptive processing. In the environment classifier implemented on Visual C++, the extraction of the parameters and selection of processing algorithm for the adaptive processing unit are possible, and the result of algorithms can be verified at each stage.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.46 no.2
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• pp.66-72
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• 2009

In this paper, an efficient frequency offset synchronization structure for OFDM(Orthogonal Frequency Division Multiplexing) is proposed. Conventional CORDIC(Coordinate Rotation Digital Computer) algorithm for frequency offset synchronization utilizes two CORDIC hardware i.e., one is vector mode for phase estimation, the other is rotation mode for compensation. But proposed structure utilizes one CORDIC hardware and divider. Through simulation, it is shown that hardware implementation complexity is reduced compared with conventional structures. The Verilog-HDL coding and front-end chip implementation results for the proposed structure show 22.1% gate count reduction comparison with those of the conventional structure.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.430-432
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• 2015

This paper describes a hardware implementation of ultra-lightweight block cipher algorithm PRESENT-80/128 that supports for two master key lengths of 80-bit and 128-bit. The PRESENT algorithm that is based on SPN (substitution and permutation network) consists of 31 round transformations. A round processing block of 64-bit data-path is used to process 31 rounds iteratively, and circuits for encryption and decryption are designed to share hardware resources. The PRESENT-80/128 crypto-processor designed in Verilog-HDL was verified using Virtex5 XC5VSX-95T FPGA and test system. The estimated throughput is about 550 Mbps with 275 MHz clock frequency.