• Proceedings of the Korean Society of Machine Tool Engineers Conference
• /
• 1996.10a
• /
• pp.144-149
• /
• 1996

The automation of mesh generation in BEM is bery important in numerical analysys field for the time and efficiency. To be solve this problem Probram and Algorithm, to achive purpose of making input data and automation of mesh generation based on Expert system is developed in this study. And function of this program can be rotating and zooming, To prove efficiency and availability of program in result the stress intensity factor which is criteria of fracture mechanics is caculated and compared with other results.

• Proceedings of the IEEK Conference
• /
• 1999.11a
• /
• pp.985-988
• /
• 1999

This paper describes the architecture and the IC implementation of a Direct Digital Frequency Synthesizer (DDFS). That is based on an angle rotation algorithm (CORDIC). It is shown that the architecture can be implemented as a multipliers, feedfoward, and easily pipelineable datapath. A prototype IC has been designed, fabricated in 0.35${\mu}{\textrm}{m}$ SAMSUNG KG90 Library.

• 제어로봇시스템학회:학술대회논문집
• /
• 1987.10b
• /
• pp.190-192
• /
• 1987

In the paper an multivariable decoupling self-tuning algorithm is proposed for controller design, by specifying the closed-loop behaviour of the system in the form of a reference model, so that the controller parameters can be estimated on-line as the process development. The effectiveness of this algorithm in controlling multivariable systems is demonstrated by simulation example in spite of the usual implementation problems of self-tuning controllers.

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.28A no.1
• /
• pp.74-84
• /
• 1991

This paper presents an algorithm for technology-dependent logic optimization and technology mapping, and describes a performance-driven logic synthesis system, SILOS, implemented based on the proposed algorithm. The system analyzes circuits and resynthesizes the critical sections such that generated circuit operates opertes within time constraints, using only gate types supported by library for direct implementation. Experimental results show that the system can be a viable tool in synthesizing high-performance logic circuits.

• Proceedings of the IEEK Conference
• /
• 2002.06e
• /
• pp.5-8
• /
• 2002

In this paper, we applied a PC interface and an embedded system in order to design a non-linear system and implement the PID algorithm as our control one. We used the inverted pendulum, one of the most generally used non-linear system models, to control uncertain factors in the environment. This paper showed how to use this non-linear system model to control the factors completely as well as to understand the PID algorithm. Furthermore, this paper applied and understood the embedded system.

• Journal of applied mathematics & informatics
• /
• v.6 no.1
• /
• pp.65-78
• /
• 1999

We present a fast/parallel Poisson solver on disks, based on efficient evaluation of the exact solution given by the Newtonian potential and the Poisson integral. Derived from an integral formula-tion it is more accurate and simpler in parallel implementation and in upgrading to a higher order algorithm than an algorithm which solves the linear system obtained from a differential formulation.

• 한국컴퓨터산업교육학회:학술대회논문집
• /
• 2003.11a
• /
• pp.111-118
• /
• 2003

Java Card API written to optimize Execute Environment in embedded device of small memory such as smart card. Java Card API intended to provide many advance when develope smart card based program. this paper purpose to implement RSA Algorithm of public key Algorithms with Java Card API.

• Annual Conference of KIPS
• /
• 2001.04b
• /
• pp.1157-1160
• /
• 2001

본 논문에서는 ATM 망에서 사용되고 있는 예방적 트래픽 제어 방법의 하나인, 사용 변수 제어(Usage Parameter Control)를 ATM 셀(Cell) 헤더(Header) 내에 있는 셀손실 우선 순위 정보(Cell Loss Priority Bit)를 기반으로 하는 개선된 UPC 알고리즘을 제안하고 그것을 구현하였다. 제안한 알고리즘은 우선순위가 높은 셀의 손실을 최소로 하고, 트래픽의 다중화 및 역다중화 과정에서 발생되는 트래픽의 군집성(Birstness of the traffic)을 해소할 수 있다는 장점을 갖고 있다.

• Proceedings of the KIEE Conference
• /
• 1988.07a
• /
• pp.165-167
• /
• 1988

In this paper, the design of decoder for R-S code using discrete finite-field Fourier transform is presented. An important ingredient of this design is a modified Euclid algorithm for computing the error-locator polynomial. The computation of inverse elements is completely avoided in this modification of Euclid algorithm. This decoder is regular and simple, and naturally suitable for VLSI implementation.

• Journal of information and communication convergence engineering
• /
• v.3 no.4
• /
• pp.201-204
• /
• 2005

Twofish is a 128-bit block cipher that accepts a variable-length key up to 256 bits. The cipher is a 16­round Feistel network with a bijective F function made up of four key-dependent 8-by-8-bit S-boxes, a fixed 4­by-4 maximum distance separable matrix over Galois Field$(GF (2^8)$, a pseudo-Hadamard transform, bitwise rotations, and a carefully designed key schedule. In this paper, the Twofish is modeled in VHDL and simulated. Hardware implementation gives much better performance than software-based approaches.