• Title/Summary/Keyword: implementation algorithm

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Searching Algorithms Implementation and Comparison of Romania Problem

  • Ismail. A. Humied
    • International Journal of Computer Science & Network Security
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    • v.24 no.9
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    • pp.105-110
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    • 2024
  • Nowadays, permutation problems with large state spaces and the path to solution is irrelevant such as N-Queens problem has the same general property for many important applications such as integrated-circuit design, factory-floor layout, job-shop scheduling, automatic programming, telecommunications network optimization, vehicle routing, and portfolio management. Therefore, methods which are able to find a solution are very important. Genetic algorithm (GA) is one the most well-known methods for solving N-Queens problem and applicable to a wide range of permutation problems. In the absence of specialized solution for a particular problem, genetic algorithm would be efficient. But holism and random choices cause problem for genetic algorithm in searching large state spaces. So, the efficiency of this algorithm would be demoted when the size of state space of the problem grows exponentially. In this paper, the new method presented based on genetic algorithm to cover this weakness. This new method is trying to provide partial view for genetic algorithm by locally searching the state space. This may cause genetic algorithm to take shorter steps toward the solution. To find the first solution and other solutions in N-Queens problem using proposed method: dividing N-Queens problem into subproblems, which configuring initial population of genetic algorithm. The proposed method is evaluated and compares it with two similar methods that indicate the amount of performance improvement.

Low-Cost AES Implementation for Wireless Embedded Systems (무선 내장형 시스템을 위한 제비용 AES의 구현)

  • LEE Dong-Ho
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.41 no.12
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    • pp.67-74
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    • 2004
  • AES is frequently used as a symmetric cryptography algorithm for the Internet. Wireless embedded systems increasingly use more conventional wired network protocols. Hence, it is important to have low-cost implementations of AES for thor The basic architecture of AES unrolls oかy one full cipher round which uses 20 S-boxes together with the key scheduler and the algorithm repeatedly executes it. To reduce the implementation cost further, the folded architecture which uses only eight S-box units was studied in the recent years. In this paper, we will study a low-cost AES implementation for wireless communication technology based on the folded architecture. We first improve the folded architecture to avoid the sixteen bytes of additional state memory. Then, we implemented a single byte architecture where only one S-box unit is used for data encryption and key scheduling. It takes 352 clocks to finish a complete encryption. We found that the maximum clock frequency of its FPGA implementation reaches about 40 MHz. It can achieve about 13 Mbps which is enough for 3G wireless communication technology.

An Efficient Hardware Implementation of Lightweight Block Cipher LEA-128/192/256 for IoT Security Applications (IoT 보안 응용을 위한 경량 블록암호 LEA-128/192/256의 효율적인 하드웨어 구현)

  • Sung, Mi-Ji;Shin, Kyung-Wook
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.19 no.7
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    • pp.1608-1616
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    • 2015
  • This paper describes an efficient hardware implementation of lightweight encryption algorithm LEA-128/192/256 which supports for three master key lengths of 128/192/256-bit. To achieve area-efficient and low-power implementation of LEA crypto- processor, the key scheduler block is optimized to share hardware resources for encryption/decryption key scheduling of three master key lengths. In addition, a parallel register structure and novel operating scheme for key scheduler is devised to reduce clock cycles required for key scheduling, which results in an increase of encryption/decryption speed by 20~30%. The designed LEA crypto-processor has been verified by FPGA implementation. The estimated performances according to master key lengths of 128/192/256-bit are 181/162/109 Mbps, respectively, at 113 MHz clock frequency.

Implementation of a Genetic Operator for Genetic Algorithm (유전자 알고리즘의 유전 연산자 구현)

  • You, Myoung-Keun;Song, Gi-Yong
    • Proceedings of the Korea Institute of Convergence Signal Processing
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    • 2005.11a
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    • pp.357-360
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    • 2005
  • 유전자 알고리즘(Genetic Algorithm, GA)은 자연적 진화과정에서 생존 경쟁 측면의 가장 적합한 메커니즘이다. GA를 소프트웨어로 수행하는데 큰 지연시간은 필수적이기 때문에 하드웨어 설계를 이용하여 알고리즘 실행 속도를 증가시키기 위한 많은 연구가 진행되어 왔다. 본 논문에서는 염색체의 임의의 유전인자를 기준으로 입력 받은 염색체에 대하여 GA 연산을 수행하는 유전 연산자를 설계한다. 설계된 디자인을 ARM 코어와 PLD로 구성된 Altera사의 Excalibur칩에 구현하여 동작을 검증하였다.

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A Low-Delay MDCT/IMDCT

  • Lee, Sangkil;Lee, Insung
    • ETRI Journal
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    • v.35 no.5
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    • pp.935-938
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    • 2013
  • This letter presents an algorithm for selecting a low delay for the modified discrete cosine transform (MDCT) and inverse MDCT (IMDCT). The implementation of conventional MDCT and IMDCT requires a 50% overlap-add (OLA) for a perfect reconstruction. In the OLA process, an algorithmic delay in the frame length is employed. A reduced overlap window and MDCT/IMDCT phase shifting is used to reduce the algorithmic delay. The performance of the proposed algorithm is evaluated by applying the low-delay MDCT to the G.729.1 speech codec.

Automation of an Interactive Interview System by Hand Gesture Recognition Using Particle Filter

  • Lee, Yang-Weon
    • Journal of information and communication convergence engineering
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    • v.9 no.6
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    • pp.633-636
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    • 2011
  • This paper describes a implementation of virtual interactive interview system. A hand motion recognition algorithm based on the particle filters is applied for this system. The particle filter is well operated for human hand motion recognition than any other recognition algorithm. Through the experiments, we show that the proposed scheme is stable and works well in virtual interview system's environments.

Introduction to Evolvable Hardware Design

  • Kim Jong O;Kim Duk Soo;Kim Young Gun
    • Proceedings of the IEEK Conference
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    • 2004.08c
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    • pp.509-513
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    • 2004
  • An area of research called evolvable hardware (EHW) has recently emerged which combines aspects of evolutionary computation with hardware design and synthesis. The features that can be used to identify and classify evolvable hardware are the evolutionary algorithm, the implementation and the genotype representation. This paper gives an introduction to the field. It continues by including classifying the EHW and the applications of the area.

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Implementation of Motion Detection of Human Under Fixed Video Camera (고정 카메라 환경하에서 사람의 움직임 검출 알고리즘의 구현)

  • 한희일
    • Proceedings of the IEEK Conference
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    • 2000.06d
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    • pp.202-205
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    • 2000
  • In this paper we propose an algorithm that detects, tracks a moving object, and classify whether it is human from the video clip captured under the fixed video camera. It detects the outline of the moving object by finding out the local maximum points of the modulus image, which is the magnitude of the motion vectors. It also estimates the size and the center of the moving object. When the object is detected, the algorithm discriminates whether it is human by segmenting the face. It is segmented by searching the elliptic shape using Hough transform and grouping the skin color region within the elliptic shape.

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PC-Based Realtime Implementation of H.263 CODEC Using SIMD Method (SIMD기법에 의한 H.263 코덱의 PC기반 실시간 구현)

  • 하교동;남수영;김남철
    • Proceedings of the IEEK Conference
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    • 2001.09a
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    • pp.947-950
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    • 2001
  • This paper implements H.263 codec using SIMD(single instruction multiple data) method in real time based on PC. This system uses INS algorithm previously proposed by the authors as motion estimation module. SIMD method is used in DCT, IDCT, quantization, motion estimation, and display module. The developed algorithms are implemented using TMN5. Using the above algorithm, H.263 Codec can communicate more than 15 frames/sec in CIF resolution on a Pentium-IV 1.7GHz computer.

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A Study on the Implementation and the Performance Evaluation of the Train Communication Network (전동차용 통신 네트워크 프로토콜 구현 및 성능평가에 관한 연구)

  • Lee, Sang-Chul;Park, Jae-Hyun;Chang, Nae-Hyuck
    • The Transactions of the Korean Institute of Electrical Engineers A
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    • v.48 no.12
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    • pp.1580-1588
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    • 1999
  • This paper evaluates the real-time performance of the Train Communication Network (TCN) that consists of WTB and MVB. A run-time scheduling algorithm for the hard-real time communication was proposed and its performance was evaluated. Also, a new addressing method and the adaptive tree algorithm were suggested to enhance performance. The overall performance was evaluated by computer simulation using Arena.

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