• Journal of the Korean Society for Marine Environment & Energy
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• v.16 no.1
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• pp.1-8
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• 2013

This study focuses on a ship detection and tracking method using Frequency Modulated Continuous Wave (FMCW) radar used for horizontal surveillance. In general, FMCW radar can play an important role in maritime surveillance, because it has many advantages such as low warm-up time, low power consumption, and its all weather performance. In this paper, we introduce an effective method for data and signal processing of ship's detecting and tracking using the X-band radar. Ships information was extracted using an image-based processing method such as the land masking and morphological filtering with a threshold for a cycle data merged from raw data (spoke data). After that, ships was tracked using search-window that is ship's expected rectangle area in the next frame considering expected maximum speed (19 kts) and interval time (5 sec). By using this method, the tracking results for most of the moving object tracking was successful and those results were compared with AIS (Automatic Identification System) for ships position. Therefore, it can be said that the practical application of this detection and tracking method using FMCW radar improve the maritime safety as well as expand the surveillance coverage cost-effectively. Algorithm improvements are required for an enhancement of small ship detection and tracking technique in the future.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.40 no.11
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• pp.51-62
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• 2003

This paper presents a novel survivor memeory management and decoding techniques with sequential backward state transition control in the trace back Viterbi decoder. The Viterbi algorithm is an maximum likelihood decoding scheme to estimate the likelihood of encoder state for channel error detection and correction. This scheme is applied to a broad range of digital communication such as intersymbol interference removing and channel equalization. In order to achieve the area-efficiency VLSI chip design with high throughput in the Viterbi decoder in which recursive operation is implied, more research is required to obtain a simple systematic parallel ACS architecture and surviver memory management. As a method of solution to the problem, this paper addresses a progressive decoding algorithm with sequential backward state transition control in the trace back Viterbi decoder. Compared to the conventional trace back decoding techniques, the required total memory can be greatly reduced in the proposed method. Furthermore, the proposed method can be implemented with a simple pipelined structure with systolic array type architecture. The implementation of the peripheral logic circuit for the control of memory access is not required, and memory access bandwidth can be reduced Therefore, the proposed method has characteristics of high area-efficiency and low power consumption with high throughput. Finally, the examples of decoding results for the received data with channel noise and application result are provided to evaluate the efficiency of the proposed method.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.37 no.5
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• pp.54-63
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• 2000

We present a multi-resolution block matching algorithm (BMA) for fast motion estimation At the coarsest level, a motion vector (MV) having minimum matching error is chosen via a full search, and a MV with minimum matching error is concurrently found among the MVs of the spatially adjacent blocks Here, to examine the spatial MVs accurately, we propose an efficient method for searching full resolution MV s without MV quantization even at the coarsest level The chosen two MV s are used as the initial search centers at the middle level At the middle level, the local search is performed within much smaller search area around each search center If the method used at the coarsest level is adopted here, the local searches can be done at integer-pel accuracy A MV having minimum matching error is selected within the local search areas, and then the final level search is performed around this initial search center Since the local searches are performed at integer-pel accuracy at the middle level, the local search at the finest level does not take an effect on the overall performance So we can skip the final level search without performance degradation, thereby the search speed increases Simulation results show that in comparison with full search BMA, the proposed BMA without the final level search achieves a speed-up factor over 200 with minor PSNR degradation of 02dB at most, under a normal MPEG2 coding environment Furthermore, our scheme IS also suitable for hardware implementation due to regular data-flow.

• Journal of Digital Contents Society
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• v.17 no.6
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• pp.581-592
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• 2016

WebRTC has quickly grown to be the world's advanced real-time communication in several platforms such as web and mobile. In spite of the advantage, the current technology in WebRTC does not handle a big-streaming efficiently between peers and a large amount request of users on the Signaling server. Therefore, in this paper, we put our work to handle the problem by delivering the flow of data with dynamical load balancing algorithms. We analyze the request source users and direct those streaming requests to a load balancing component. More specifically, the component determines an amount of the requested resource and available resource on the response server, then it delivers streaming data to the requesting user parallel or alternately. To show how the method works, we firstly demonstrate the load-balancing algorithm by using a network simulation tool OPNET, then, we seek to implement the method into an Ubuntu server. In addition, we compare the result of our work and the original implementation of WebRTC, it shows that the method performs efficiently and dynamically than the origin.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.11 no.10
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• pp.4717-4737
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• 2017

Today, smart grids, smart homes, smart water networks, and intelligent transportation, are infrastructure systems that connect our world more than we ever thought possible and are associated with a single concept, the Internet of Things (IoT). The number of devices connected to the IoT and hence the number of traffic flow increases continuously, as well as the emergence of new applications. Although cutting-edge hardware technology can be employed to achieve a fast implementation to handle this huge data streams, there will always be a limit on size of traffic supported by a given architecture. However, recent cloud-based big data technologies fortunately offer an ideal environment to handle this issue. Moreover, the ever-increasing high volume of traffic created on demand presents great challenges for flow management. As a solution, flow aggregation decreases the number of flows needed to be processed by the network. The previous works in the literature prove that most of aggregation strategies designed for smart grids aim at optimizing system operation performance. They consider a common identifier to aggregate traffic on each device, having its independent static aggregation policy. In this paper, we propose a dynamic approach to aggregate flows based on traffic characteristics and device preferences. Our algorithm runs on a big data platform to provide an end-to-end network visibility of flows, which performs high-speed and high-volume computations to identify the clusters of similar flows and aggregate massive number of mice flows into a few meta-flows. Compared with existing solutions, our approach dynamically aggregates large number of such small flows into fewer flows, based on traffic characteristics and access node preferences. Using this approach, we alleviate the problem of processing a large amount of micro flows, and also significantly improve the accuracy of meeting the access node QoS demands. We conducted experiments, using a dataset of up to 100,000 flows, and studied the performance of our algorithm analytically. The experimental results are presented to show the promising effectiveness and scalability of our proposed approach.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.7
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• pp.1296-1302
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• 2016

A hardware implementation of ultra-lightweight block cipher algorithm PRESENT that was specified as a block cipher standard for lightweight cryptography ISO/IEC 29192-2 is described in this paper. Two types of crypto-core that support master key size of 80-bit are designed, one is for encryption-only function, and the other is for encryption and decryption functions. The designed PR80 crypto-cores implement the basic cipher mode of operation ECB (electronic code book), and it can process consecutive blocks of plaintext/ciphertext without reloading master key. The PR80 crypto-cores were designed in soft IP with Verilog HDL, and they were verified using Virtex5 FPGA device. The synthesis results using $0.18{\mu}m$ CMOS cell library show that the encryption-only core has 2,990 GE and the encryption/decryption core has 3,687 GE, so they are very suitable for IoT security applications requiring small gate count. The estimated maximum clock frequency is 500 MHz for the encryption-only core and 444 MHz for the encryption/decryption core.

• Journal of KIISE
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• v.44 no.2
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• pp.115-123
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• 2017

A message processor is server software that receives non-realtime messages as well as realtime messages from clients that need to be processed within a deadline. With the recent advances of micro-processor technologies and Linux, the message processor is often implemented in Linux-based multi-core servers and it is important to use cores efficiently to maximize the performance of system in multi-core environments. Numerous research efforts on a real-time scheduler for the efficient utilization of the multi-core environments have been conducted. Typically, though, they have been conducted theoretically or via simulation, making a subsequent real-system application difficult. Moreover, many Linux-based real-time schedulers can only be used in a specific Linux version, or the Linux source code needs to be modified. This paper presents the design of a Linux-based message processor for multi-core environments that maps the threads to the cores at user level. The message processor is implemented through a modification of the traditional RM algorithm that consolidates the real-time messages into certain cores using a first-fit-based bin-packing algorithm; this minimizes the response-time delay of the non-real-time messages, while guaranteeing the violation rate of the real-time messages. To compare the performances, the message processor was implemented using the two multi-core-scheduling algorithms GSN-EDF and P-FP, which are provided by the LITMUS framework. The benchmarking results show that the response-time delay of non-real-time messages in the proposed system was improved up to a maximum of 17% to 18%.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.11
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• pp.32-40
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• 2016

IEEE 802.15.4 is the one of the protocols for radio communication in a personal area network. Because of low cost and low power communication for IoT communication, it requires the highest optimization level in the implementation. Recently, the studies of location aware algorithm based on IEEE802.15.4 standard has been achieved. Location estimation is performed basically in equal consideration of reference node information and blind node information. However, an error is not calculated in this algorithm despite the fact that the coordinates of the estimated location of the blind node include an error. In this paper, we enhanced a conventual maximum likelihood estimation using weighted coefficient and implement the hardwired location aware engine for small code size and low power consumption. On the field test using test-beds, the suggested hardware based location awareness method results better accuracy by 10 percents and reduces both calculation and memory access by 30 percents, which improves the systems power consumption.

• Journal of the Korean Society of Surveying, Geodesy, Photogrammetry and Cartography
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• v.37 no.6
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• pp.445-452
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• 2019

In this study, parallel processing codes of k-means clustering algorithm were developed and implemented in a PC-cluster for unsupervised classification of large satellite images. We implemented intra-node code using multicores of CPU (Central Processing Unit) based on OpenMP (Open Multi-Processing), inter-nodes code using a PC-cluster based on message passing interface, and hybrid code using both. The PC-cluster consists of one master node and eight slave nodes, and each node is equipped with eight multicores. Two operating systems, Microsoft Windows and Canonical Ubuntu, were installed in the PC-cluster in turn and tested to compare parallel processing performance. Two multispectral satellite images were tested, which are a medium-capacity LANDSAT 8 OLI (Operational Land Imager) image and a high-capacity Sentinel 2A image. To evaluate the performance of parallel processing, speedup and efficiency were measured. Overall, the speedup was over N / 2 and the efficiency was over 0.5. From the comparison of the two operating systems, the Ubuntu system showed two to three times faster performance. To confirm that the results of the sequential and parallel processing coincide with the other, the center value of each band and the number of classified pixels were compared, and result images were examined by pixel to pixel comparison. It was found that care should be taken to avoid false sharing of OpenMP in intra-node implementation. To process large satellite images in a PC-cluster, code and hardware should be designed to reduce performance degradation caused by file I / O. Also, it was found that performance can differ depending on the operating system installed in a PC-cluster.

• Journal of Korea Multimedia Society
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• v.14 no.7
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• pp.895-904
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• 2011

In welding machine that executes existing spot welding, wrong operation of system has often occurs because of their mechanical motion that can be caused by a number of supply like the welding object. In exposed working environment for various situations such as worker or related equipment moving into any place that we are unable to exactly distinguish between good and not condition of nut. Also, in case of defective welding of nut, it needs various evaluation and analysis through image processing because the problem that worker should be inspected every single manually. Therefore in this paper, if the object was not stabilization state correctly, we have purpose to algorithm implementation that it is to reduce the analysis time and exact recognition as to improve system of image processing. As this like, as image analysis for assessment whether it is good or not condition of nut, in his paper, implemented algorithms were suggested and list by group and that it showed the effectiveness through more than one experiment. As the result, recognition rate of normality and error according to the estimation time have been shown as 40%~94.6% and 60%~5.4% from classification 1 of group 1 to classification 11 of group 5, and that estimation time of minimum, maximum, and average have been shown as 1.7sec.~0.08sec., 3.6sec.~1.2sec., and 2.5sec.~0.1sec.