• Title/Summary/Keyword: implementation algorithm

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The Implementation of the Built-In Self-Test for AC Parameter Testing of SDRAM (SDRAM 의 AC 변수 테스트를 위한 BIST구현)

  • Sang-Bong Park
    • The Journal of Information Technology
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    • v.3 no.3
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    • pp.57-65
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    • 2000
  • We have proposed BIST method and circuit for embedded 16M SDRAM with logic. It can test the AC parameter of embedded 16M SDRAM using the BIST circuit capable of detecting the address of a fail cell of a 16M SDRAM installed in an Merged Memory with Logic(MML) generating the information of repair for redundancy circuit. The function and AC parameter of the embedded memory can also be tested using the proposed BIST method. The total gate of the BIST circuit is approximately 4,500 in the case of synthesizing by $0.25\mu\textrm{m}$ cell library. and verify the result of Verilog simulation. The test time of each one AC parameter is about 200ms using 2Y-March 14N algorithm.

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The Development of Compensated Bang-Bang Current Controller for Travel Motor of Industry Electrical Vechicle (산업용 전기차량의 주행 모터용 보상된 Bang-Bang 전류제어기 개발)

  • Chen, Young-Shin;Jung, Young-Il;Bae, Jong-Il;Lee, Man-Hyung
    • Journal of the Korean Society for Precision Engineering
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    • v.16 no.9
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    • pp.34-40
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    • 1999
  • In order to establish the design technique of the robust current controller in d.c series wound motor driver system, this paper proposes a method of the compensated Bang-Bang current control using d.c series wound motor driver system under the improperly variable load to get minimum time for the torque control. The compensated Bang-Bang current controller structure is simpler than that of PID plus Bang-Bang controller. This paper shows that a general 16 bits microprocessor is efficiently used to implement such an algorithm. The calculation time of software is extremely small when compared with that of conventional PID plus Bang-Bang controller. Both nonlinear operating characteristics of digital switching elements and describing function methods are used for the analysis and synthesis. Real-time implementation of the compensated Bang-Bang current controller is achieved. The concept of design strategy of the control and the PWM waveform generation algorithms are presented in this paper.

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Towards Designing Efficient Lightweight Ciphers for Internet of Things

  • Tausif, Muhammad;Ferzund, Javed;Jabbar, Sohail;Shahzadi, Raheela
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.11 no.8
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    • pp.4006-4024
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    • 2017
  • Internet of Things (IoT) will transform our daily life by making different aspects of life smart like smart home, smart workplace, smart health and smart city etc. IoT is based on network of physical objects equipped with sensors and actuators that can gather and share data with other objects or humans. Secure communication is required for successful working of IoT. In this paper, a total of 13 lightweight cryptographic algorithms are evaluated based on their implementation results on 8-bit, 16-bit, and 32-bit microcontrollers and their appropriateness is examined for resource-constrained scenarios like IoT. These algorithms are analysed by dissecting them into their logical and structural elements. This paper tries to investigate the relationships between the structural elements of an algorithm and its performance. Association rule mining is used to find association patterns among the constituent elements of the selected ciphers and their performance. Interesting results are found on the type of element used to improve the cipher in terms of code size, RAM requirement and execution time. This paper will serve as a guideline for cryptographic designers to design improved ciphers for resource constrained environments like IoT.

The Design and Implementation of the Adaptive Contrast Controller System (적응형 콘트라스트 제어 시스템의 설계 및 구현)

  • 김철순;권병헌;곽경섭
    • Journal of Korea Multimedia Society
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    • v.5 no.1
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    • pp.38-46
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    • 2002
  • In this paper, we present an adaptive contrast controller for improving the Quality of motion-picture in the video signals on the display. Using a median of image signals, we can improve the contrast according to the middle brightness, adaptively. In addition, the proposed method is useful for real-time image processing and can be composed of simpler hardware structure than other conventional methods because it does not require field and frame memory for computed data. The proposed method can be applied for video signals as well as the still image, while existing methods are confined to only the static image Also, we designed the algorithm through the VHDL, and implemented it through the FPGA. From the testing results, we see that the proposed method can effectively improve the image contrast.

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Hardware Implementation for Stabilization of Detected Face Area (검출된 얼굴 영역 안정화를 위한 하드웨어 구현)

  • Cho, Ho-Sang;Jang, Kyoung-Hoon;Kang, Hyun-Jung;Kang, Bong-Soon
    • Journal of the Institute of Convergence Signal Processing
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    • v.13 no.2
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    • pp.77-82
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    • 2012
  • This paper presents a hardware-implemented face regions stabilization algorithm that stabilizes facial regions using the locations and sizes of human faces found by a face detection system. Face detection algorithms extract facial features or patterns determining the presence of a face from a video source and detect faces via a classifier trained on example faces. But face detection results has big variations in the detected locations and sizes of faces by slight shaking. To address this problem, the high frequency reduce filter that reduces variations in the detected face regions by taking into account the face range information between the current and previous video frames are implemented in addition to center distance comparison and zooming operations.

Design and Implementation of Efficient Adaptive RED Router Suffer Management Algorithm (Efficient Adaptive RED라우터 버퍼 관리 알고리즘 디자인과 구현)

  • Lee, Jong-Hyun;Lim, Hye-Young;Huh, Eui-Nam;Hwang, Jun;Kim, Young-Chan
    • Proceedings of the Korean Information Science Society Conference
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    • 2003.04d
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    • pp.208-210
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    • 2003
  • RED(Random Early Detection) 라우터를 성공적으로 배치하기 위해서는 RED 알고리즘을 구성하는 각 파라미터를 적절히 조절할 수 있어야 한다. 특히 다수의 TCP 연결이 하나의 라우터를 공유하는 네트워크 병목구간에서는 그 중요성이 한층 강조된다. 그러나 RED가 TD 라우터와 같은 네트워크 퍼포먼스를 유지하면서 ICP 커넥션 간 페어니스(fairness)를 향상시키기 위해서는, 네트워크 상황에 따라 다수의 컨트롤 파라미터 값을 적절하게 설정해줘야만 한다. 문제는 다양한 네트워크 환경에서 효과적으로 RED 알고리즘이 동작하기 위해 파라미터를 설정하는 것이 매우 어렵다는 것이다. 본 논문에서는 네트워크 상황에 따라 동적으로 RED 파라미터를 조절하면서 빠르게 안정적인 상태로 적응하는 진보된 RED 알고리즘인 ea-RED(Efficient Adaptive RED)를 디자인하고 구현하여 알고리즘의 효율성을 확인한다.

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Design and Implementation of Margin Push Multi-agent System using Margin Generation Algorithm (마진 생성 알고리즘을 이용한 마진 푸쉬 멀티 에이전트 시스템 설계 및 구현)

  • Kim, Jung-Jae;Hu, Jae-Hyung;Lee, Jong-Hee;Oh, Hae-Seok
    • Annual Conference of KIPS
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    • 2001.04a
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    • pp.465-468
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    • 2001
  • 현재 전자상거래에서의 이용률이 저조한 경매시스템을 지능적인 소프트웨어 에이전트를 이용하여 사용자 측면에서 더욱 효율적이고 효과적인 경매시스템을 연구 및 개발은 커다란 이슈가 되고 있다. 따라서, 단순한 게시판 형식의 인터넷 경매 시스템의 인공지능 에이전트를 도입하여 해당 경매 상품에 대해 판매자에게 적정한 경매 시기와 초기값을 계산 및 예측하여 최대한의 마진을 남길 수 있도록 해주는 에이전트 시스템의 연구가 본 논문의 목적이다. 상품을 인터넷 경매에 올리는 판매자가 판매 하고자 하는 경매 상품에 대한 정보를 인터넷 경매 시스템의 에이전트에게 메일로 보내면 에이전트는 해당 상품과 유사한 상품에 대해 필터링하여 이미 학습되어져 있는 유사 상품에 대한 정보 즉, 데이터베이스에 저장되어 있는 경매 상품에 대한 입찰 히스토리와 경매시간, 경매방법, 낙찰가격 등을 계산하여 해당 상품에 대해 판매자가 어느 시기에 얼마의 초기 가격으로 경매를 시작하면 최대한의 마진을 남길 수 있는지에 대해 정보를 메일로 푸쉬해 주는 시스템을 설계 및 구현한다.

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Design and Implementation of UV Flame Detector Module Using Low Power Algorithm of ZigBee (ZigBee Protocol의 저 전력 알고리듬을 이용한 UV Flame Detector의 설계 및 구현)

  • Lee, Young-Jae;Chang, Choong-Won;Rhee, Sang-Yong;Jung, Min-Su
    • Journal of the Korean Institute of Intelligent Systems
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    • v.18 no.3
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    • pp.429-436
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    • 2008
  • Nowadays fires must be detected rapidly Abstract, and by connecting the detector's distribution, sender, transponder, receiver and others can be connected. Mechanical systems are implemented in today's buildings. However, this kind of constructing method has some disadvantages, that is, if fire happens somewhere, we cannot judge where the fires happen, and it is also difficult to judge what extent the fires reach. In order to overcome the disadvantages, in this paper, according to the tendency of combining the Ubiquitous and Intelligent Network, we propose a type of system by using the method of comparing the differences of the existed systems. The proposed system is designed to perceive the fires rapidly and confirm the fire place and fire scale correctly.

FPGA Implementation of Doppler Invarient Low Power BFSK Receiver Using CORDIC (CORDIC을 이용한 도플러 불변 저전력 BFSK 수신기의 FPGA구현)

  • Byon, Kun-Sik
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.12 no.8
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    • pp.1488-1494
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    • 2008
  • This paper is to design and implement a low power noncoherent BFSK receiver intended for future deep space communication using Xilinx System generator. The receiver incorporates a 16 point Fast Fourier Transform(FFT) for symbol detection. The design units of the receiver are digital design for better efficiency and reliability. The receiver functions on one bit data processing and supports main data rate 10kbps. In addition CORDIC algorithm is used for avoiding complex multiplications while computing FFT and multiplication of twiddle factor for low power is substituted by rotators. The design and simulation of the receiver is carried out in Simulink then the Simulink model is translated to the hardware model to implement FPGA using Xilinx System Generator and to verify performance.

An Implementation of ISP for CMOS Image Sensor (CMOS 카메라 이미지 센서용 ISP 구현)

  • Sonh, Seung-Il;Lee, Dong-Hoon
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.11 no.3
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    • pp.555-562
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    • 2007
  • In order to display Bayer input stream received from CMOS image sensor to the display device, image signal processing must be performed. That is, the hardware performing the image signal processing for Bayer data is called ISP(Image Signal Processor). We can see real image through ISP processing. ISP executes functionalities for gamma correction, interpolation, color space conversion, image effect, image scale, AWB, AE and AF. In this paper, we obtained the optimum algorithm through software verification of ISP module for CMOS camera image sensor and described using VHDL and verified in ModelSim6.0a simulator. Also we downloaded into Xilinx XCV-1000e for the designed ISP module and completed the board level verification using PCI interface.