• Proceedings of the KIEE Conference
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• 2006.10a
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• pp.224-226
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• 2006

In this paper, we have studied for analysis of the partial discharge(PD) signal in power transmission line. The PD signal has estimated as detected signal accumulation of a PRPDA method by using Labview, and analyzed with neuro-fuzzy algorithm. With practical PD logic implementation of theoretical detected system and hardware implementation, the device for Hipotronics Company's 22.9kV or 154kV setup has generated and then has applied with 18kV,20kV with 1:1 time probe. It's also used the LDPE O.27mmt (scratch error O.05mmt) to sample for making PD. Our new class of PD detected algorithm has also compared with previous PRPDA or Fuzzy algorithm, which has diagnose more conveniently by adding numerical values.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.55 no.5
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• pp.179-184
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• 2006

In a power system, an out-of-step condition causes a variety of risk such as serious damage to system elements, tripping of loads and generators, mal-operation of relays, etc. Therefore, it is very important to detect the out-of- step condition and take a proper measure. This paper presents a study on implementation of out-of-step detection algorithm using VHDL(Very high speed Hardware Description Language). The structure of out-of-step detection algorithm is analyzed for development of out-of-step detection relay on the FPGA(Field Programmable Gate Array). The out-of-step algorithm is separated to 4 parts: DFT IP, complex power calculation IP, out-of-step detection IP, control unit. Each parts are developed and simulated by using VHDL.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.3 no.1
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• pp.69-74
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• 1999

This paper describes the principles of IDEA(international data encryption algorithm) which has been widely accepted as a data encryption algorithm and the implementation of the algorithm on the TMS320C54X DSP board is addressed. It is also shown that the processing time is significantly reduced by adapting high speed multiplication modulo (2^16+1) algorithm. The result shows data rates of about 250∼300Mbyte/sec.

• Journal of the Institute of Convergence Signal Processing
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• v.3 no.1
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• pp.87-92
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• 2002

Placement is an important step in the physical design of VLSI circuits. It is the problem of placing a set of circuit modules on a chip to optimize the circuit performance. The most popular algorithms for placement include the cluster growth, simulated annealing and integer linear programming. In this paper we propose a stochastic evolution algorithm searching solution space for the placement problem, and then compare it with simulated annealing by analyzing the results of each implementation.

• Proceedings of the KIEE Conference
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• 2007.07a
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• pp.1445-1446
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• 2007

In this paper, we have studied for analysis of the partial discharge(PD) signal in power transmission line. The PD signal has estimated as detected signal accumulation of a PRPDA method by using Labview, and analyzed with neural-fuzzy algorithm. With practical PD logic implementation of theoretical detected system and hardware implementation, the device for Hipotronics Company's 22.9kV or 154kV setup have generated and then have applied with 18kV,20kV with 1:1 time probe. It's also used the LDPE 0.27mmt (scratch error 0.05mmt) to sample for making PD. Our new class of PD detected algorithm have also compared with previous PRPDA or Neural Fuzzy algorithm, which has diagnose more conveniently by adding numerical values.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2016.10a
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• pp.202-205
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• 2016

Shipping and logistics safety, security system is strengthening worldwide, the development of shipping and logistics safety security core technology for national security logistics system construction has been carried out. Interest in portable radiation detection device capable detecting gamma rays nuclides is increasing. In this paper, I would like to propose the study of implementation of digital portable radiation detector with the algorithm of temperature compensation.

• IEMEK Journal of Embedded Systems and Applications
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• v.18 no.5
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• pp.209-215
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• 2023

This study proposes an AC servo motor control program structure and its implementation method to efficiently integrate 13 types of additional compensation algorithms into the basic FOC (field-oriented control) algorithm program. Various compensation algorithms are necessary to enhance the stability and performance of machine tools by compensating for interference from disturbances and vibrations. Each compensation algorithm is implemented as a separate, independent function and called from a switch-case statement in the ISR (interrupt service routine) of the PWM (pulse-width modulation) device. The advantages of this approach include facilitating not only debugging and testing but also reducing the possibility of errors during the program development phase. Thus, it is easy to add and activate each specific compensation algorithm for the program update during the program operation phase. The implemented motor control program was experimented with a single-axis feed shaft testbed driven by a commercial AC servo motor control drive board and a 750 Watts SPMSM (surface-mounted permanent magnet synchronous motor), and the results verified its normal operation and performance improvement.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.40 no.6
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• pp.118-126
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• 2003

This paper presents a low-complexity algorithm lot browsing a HD bit stream in DTV PVR according to its characteristics and also presents its implementation results. We propose an efficient algorithm which detects shots using some information after decoding MPEG-2 data, clusters them into scene and episode, and intelligently browses them according to some criteria after calculating their complexity. Some simulation results are presented to show the performance feasibility of the proposed algorithm. To implement it in real time, we propose an efficient hybrid architecture which partitions the algorithm into two parts of hardware and software. The hardware covers decoding process and extraction of some basic information which take most complexity in implementing the algorithm. The software covers the heuristic part of tile algorithm which has low complexity and needs to be expandable.

• Journal of The Institute of Information and Telecommunication Facilities Engineering
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• v.5 no.1
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• pp.25-36
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• 2006

This paper discusses the implementation and performance evaluation of a DSP-based digital beamformer using the Texas Instrument TMSC6711 DSP processor for smart antenna applications. Two adaptive beamforming algorithms which served as the brain for the beamformer, the Normalized Least-Mean-Square (NLMS) and the Constant Modulus Algorithms (CMA) were embedded into the processor and evaluated. Result shows that the NLMS-based digital beamformer outperforms the CMA-based digital beamformer: 1)For NLMS algorithm, the antenna steers to the direction of the desired user even at low iteration value and the suppression level towards the interferer increases as the number of iteration increase. For CMA algorithm, the beam radiation pattern slowly steers to the desired user as the number of iteration increased, but at arate slower than NLMS algorithm and the sidelobe level is shown to increases as the number of iteration increase. 2) The NLMS algorithm has faster convergence than CMA algorithm and the error convergence for CMA algorithm sometimes is subject to misadjustment.

• 전자공학회논문지 IE
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• v.46 no.2
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• pp.7-10
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• 2009

This paper presents the implementation of libraries of hardware modules for genetic algorithm using VHDL. Evolvable hardware refers to hardware that can change its architecture and behavior dynamically and autonomously by interacting with its environment. So, it is especially suited to applications where no hardware specifications can be given in advance. Evolvable hardware is based on the idea of combining reconfigurable hardware device with evolutionary computation, such as genetic algorithm. Because of parallel, no function call overhead and pipelining, a hardware genetic algorithm give speedup over a software genetic algorithm. This paper suggests the hardware genetic algorithm for evolvable embedded system chip. That includes simulation results and analysis for several fitness functions. It can be seen that our design works well for the three examples.