• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.10a
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• pp.661-664
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• 2003

Trade-off of sorority and speed always exists in the latest network environment. Recently, developed security processors is improved very performance, and sorority connection algorithms of a lot of part were embodied by hardware. This high speed security processor is essential ingredient in string network security solution equipment development that require very big band width. In this paper, we wish to describe about design and implementation of 10 Giga VPN equipments. In this system, embodied 10 Giga to use Cavium company's Nitrox-II processor, and supports two SP14-2 interface and PCI interface. All of the password algorithm that password algorithm that support is used in common use VPN equipment for compatibility with common use VPN equipment are supported and support SEED algorithm developed in domestic. Designed to support IPsec and SSL protocol, and supports all of In-Line structure that is profitable in high speed transaction and the Look-Aside structure that is profitable in practical use degree of NPU(Network Processor Unit).

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.10
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• pp.1981-1989
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• 2017

In accordance with the global strengthening of security systems for the safety of the shipping and logistics industry, the development of core technologies within the field has become a key in the establishment of Korea's own national logistics security system. Further in line with these global developments, there is growing attention within Korea to the development of portable radiation detectors capable of detecting gamma ray nuclides. In addition, many parts are becoming localized. In this research, instead of Pulse Shaping Board, which is used in existing portable radiation detectors, we have implemented an Algorithm to discriminate nuclides and correct the temperature conversion efficiency of the scintillator. This paper aims to improve the performance of these devices through the implementation of a temperature conversional algorithm within the scintillator of the A9-based digital portable radiation detector.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37 no.6B
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• pp.405-413
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• 2012

WFQ(Weighted Fair Queuing) is the most popular fair queuing algorithm to guarantee the Quality-of-Service(QoS), but it has the inherent drawback of a poor resource utilization, particularly under the low rate traffic requiring a tight delay bound. It was recently identified that the poor utilization is mainly due to non-optimized latency of a traffic flow and then LOFQ(Latency-Optimized Fair Queuing) to overcome the drawback was introduced. The LOFQ algorithm, however, renews their optimal latencies for all flows whenever a new flow arrives, which results in the high implementation complexity of O($N^2$).This paper is to reduce thecomplexity to O(1). The proposed method is first to derive the optimal latency index function from the statistical QoS characteristics of the offered load, and then to simply calculate the optimal latency index of the arriving flow using the function.

• Journal of the Institute of Convergence Signal Processing
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• v.14 no.3
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• pp.162-168
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• 2013

This paper examines the implementation of automatic compensation modules for digital camera image when a person is closing his/her eyes. The modules detect the face and eye region and then recognize the eye state. If the image is taken when a person is closing his/her eyes, the function corrects the eye and produces the image by using the most satisfactory image of the eye state among the past frames stored in the buffer. In order to recognize the face and eye precisely, the pre-process of image correction is carried out using SURF algorithm and Homography method. For the detection of face and eye region, Haar-like feature algorithm is used. To decide whether the eye is open or not, similarity comparison method is used along with template matching of the eye region. The modules are tested in various facial environments and confirmed to effectively correct the images containing faces.

• The Journal of the Korea institute of electronic communication sciences
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• v.13 no.1
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• pp.169-174
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• 2018

There are many CCTV cameras connected to the video surveillance and monitoring center for the safety of citizens, and it is difficult for a few monitoring agents to monitor many channels of videos. In this paper, we propose an intelligent video surveillance system utilizing a safety map to efficiently monitor many channels of CCTV camera videos. The safety map establishes the frequency of crime occurrence as a database, expresses the degree of crime risk and makes it possible for agents of the video surveillance center to pay attention when a woman enters the crime risk area. The proposed gender classification method is processed in the order of pedestrian detection, tracking and classification with deep training. The pedestrian detection and tracking uses Adaboost algorithm and probabilistic data association filter, respectively. In order to classify the gender of the pedestrian, relatively simple AlexNet is applied to determine gender. Experimental results show that the proposed gender classification method is more effective than the conventional algorithm. In addition, the results of implementation of intelligent video security system combined with safety map are introduced.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.10
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• pp.2443-2450
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• 2014

In the motion recognition system using depth image, the depth image is converted to the real world formed 3D point cloud data for efficient algorithm apply. And then, output depth image is converted by the projective world after algorithm apply. However, when coordinate conversion, rounding error and data loss by applied algorithm are occurred. In this paper, when convert 3D point cloud data to depth image, we proposed efficient conversion method and its hardware implementation without rounding error and data loss according image size change. The proposed system make progress using the OpenCV and the window program, and we test a system using the Kinect in real time. In addition, designed using Verilog-HDL and verified through the Zynq-7000 FPGA Board of Xilinx.

• Journal of Advanced Navigation Technology
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• v.14 no.6
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• pp.996-1001
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• 2010

In this paper, network selection algorithm for services of mobile IPTV(internet protocol television) and implementation of a hierarchical processing system for reducing overload by terminal with low speed is proposed. This algorithm selects the network according to the following priorities derived from formulas; value that uses remaining bandwidth, network cost, signal strength. If terminal has a low processing power for using selected network and TV service, quality of service declines due to the system overloading. Hence, we implemented system which processes selected network and TV services accomplished by layer divided. Through experiments results, the method of direct user network selection waits for bandwidth assignment. However, on the one hand, that waiting time in exhausted situation will be very long. On the other hand, if we consider the priority plot of used networks, we should select the network with the best state. Therefore, data transmission rate will keep on average and the waiting time will be low.

• KIPS Transactions on Software and Data Engineering
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• v.2 no.3
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• pp.199-204
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• 2013

An implementation method of real-time numeral recognizer based on gesture is presented in this paper for various information devices. The proposed algorithm steadily captures the motion of a hand on 3D open space with the Kinect sensor. The captured hand motion is simplified with PCA, in order to preserve the trace consistency and to minimize the trace variations due to noises and size changes. In addition, we also propose a new HMM using both the gradient and the positional features of the simplified hand stroke. As the result, the proposed algorithm has robust characteristics to the variations of the size and speed of hand motion. The recognition rate is increased up to 30%, because of this combined model. Experimental results showed that the proposed algorithm gives a high recognition rate about 98%.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.12 no.3
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• pp.186-191
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• 2019

In this paper, we propose a implementation approach of the high-speed feature extraction algorithm. The proposed method is based on the block type classification algorithm which reduces the computation time when target macro block is divided to smooth block type that has no image features. It is quantitatively identified that occurs at 29.5% of the total image using 200 standard test images with $64{\times}64$ macro block size. This means that within a standard test image containing various image information, 29.5% can reduce the complexity of the operation. When the proposed approach is applied to the Canny edge detection, the required latency of the edge detection can be completely eliminated, such as 2D derivative filter, gradient magnitude/direction computation, non-maximal suppression, adaptive threshold calculation, hysteresis thresholding. Also, it is expected that operation time of the feature detection can be reduced by applying block type classification algorithm to various feature extraction algorithms in this way.

• Journal of IKEEE
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• v.22 no.4
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• pp.886-895
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• 2018

This paper describes a hardware design of the Secure Hash Algorithm-3 (SHA-3) hash functions that are the latest version of the SHA family of standards released by NIST, and an implementation of ARM Cortex-M0 interface for security SoC applications. To achieve an optimized design, the tradeoff between hardware complexity and performance was analyzed for five hardware architectures, and the datapath of round block was determined to be 1600-bit on the basis of the analysis results. In addition, the padder with a 64-bit interface to round block was implemented in hardware. A SoC prototype that integrates the SHA-3 hash processor, Cortex-M0 and AHB interface was implemented in Cyclone-V FPGA device, and the hardware/software co-verification was carried out. The SHA-3 hash processor uses 1,672 slices of Virtex-5 FPGA and has an estimated maximum clock frequency of 289 Mhz, achieving a throughput of 5.04 Gbps.