• Title/Summary/Keyword: impedance network

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High-Frequency Equivalent Circuit Model for Differential Mode Noise Analysis of DC-DC Buck Converter (DC-DC 벅 컨버터의 차동모드 노이즈 분석을 위한 고주파 등가회로 모델)

  • Shin, Juhyun;Kim, Woojung;Cha, Hanju
    • KEPCO Journal on Electric Power and Energy
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    • v.6 no.4
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    • pp.473-480
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    • 2020
  • In this paper, we proposed a high frequency equivalent circuit considering parasitic impedance components for differential noise analysis on the input stage during DC-DC buck converter switching operation. Based on the proposed equivalent circuit model, we presented a method to measure parasitic impedance parameters included in DC bus plate, IGBT, and PCB track using the gain phase method of a network analyzer. In order to verify the validity of this model, a DC-DC prototype consisting of a buck converter, a signal analyzer, and a LISN device, and then resonance frequency was measured in the frequency range between 150 kHz and 30 MHz. The validity of the parasitic impedance measurement method and the proposed equivalent model is verified by deriving that the measured resonance frequency and the resonance frequency of the proposed high frequency equivalent model are the same.

Design of a broadband(2㎓-5.8㎓) FET Switch Using Impedance Transformation Network (임피던스 변환회로를 이용한 광대역(2㎓-5.8㎓) FET 스위치 설계)

  • 노희정
    • Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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    • v.18 no.4
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    • pp.155-159
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    • 2004
  • This paper describes the design and the simulation of a single pole double throw(SPDT) FET switch for wireless LAN(IEEE802.11a & IEEE802.11b) applications using drain impedance transformation network with Microstrip transmission line. At the receiving path insertion losses were from 0.8(㏈) to 1.462(㏈) between 2(㎓) and 4(㎓), from l.26(㏈) to 2.3(㏈) between 4.7(㎓) and 6.7(㎓) and the isolations were under 30(㏈) between 2(㎓) and 6.7(㎓). At the transmitting path insertion loss were from 1.18(㏈) to 2.87(㏈) between 2(㎓) and 4(㎓) from 0.625(㏈) to 1.2(㏈) between 4.7(㎓) and 6.7(㎓) and the isolations were under 30(㏈) between 2(㎓) and 6.7(㎓).

A Framework for Wide-area Monitoring of Tree-related High Impedance Faults in Medium-voltage Networks

  • Bahador, Nooshin;Matinfar, Hamid Reza;Namdari, Farhad
    • Journal of Electrical Engineering and Technology
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    • v.13 no.1
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    • pp.1-10
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    • 2018
  • Wide-area monitoring of tree-related high impedance fault (THIF) efficiently contributes to increase reliability of large-scaled network, since the failure to early location of them may results in critical lines tripping and consequently large blackouts. In the first place, this wide-area monitoring of THIF requires managing the placement of sensors across large power grid network according to THIF detection objective. For this purpose, current paper presents a framework in which sensors are distributed according to a predetermined risk map. The proposed risk map determines the possibility of THIF occurrence on every branch in a power network, based on electrical conductivity of trees and their positions to power lines which extracted from spectral data. The obtained possibility value can be considered as a weight coefficient assigned to each branch in sensor placement problem. The next step after sensors deployment is to on-line monitor based on moving data window. In this on-line process, the received data window is evaluated for obtaining a correlation between low frequency and high frequency components of signal. If obtained correlation follows a specified pattern, received signal is considered as a THIF. Thereafter, if several faulted section candidates are found by deployed sensors, the most likely location is chosen from the list of candidates based on predetermined THIF risk map.

Designing Impedance Network at Quasi Z-Source Inverters by Considering ESR in the Capacitor (커패시터의 ESR을 고려한 Quasi Z-소스 인버터의 임피던스 네트워크 설계)

  • Yang, Jong-Ho;Chun, Tae-Won;Lee, Hong-Hee;Kim, Heung-Geun;Nho, Eui-Cheol
    • The Transactions of the Korean Institute of Power Electronics
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    • v.17 no.5
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    • pp.453-460
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    • 2012
  • This paper proposes the method to design the parameters of an impedance network at three-phase QZSI(quasi Z-source inverter) by considering an equivalent series resistance (ESR) in the capacitor. The equations of both two capacitor voltages and two inductor currents are derived at three operating modes of the QZSI. The capacitor voltage ripples caused by the ESR in the capacitor at the transition state of operating modes are calculated. Based on the ripples of both the capacitor voltages and inductor currents, the optimal values of capacitor and inductor are designed. The simulation studies using PSIM and experimental results with DSP are carried out to verify the performance of design method.

A study on estimating the interlayer boundary of the subsurface using a artificial neural network with electrical impedance tomography

  • Sharma, Sunam Kumar;Khambampati, Anil Kumar;Kim, Kyung Youn
    • Journal of IKEEE
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    • v.25 no.4
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    • pp.650-663
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    • 2021
  • Subsurface topology estimation is an important factor in the geophysical survey. Electrical impedance tomography is one of the popular methods used for subsurface imaging. The EIT inverse problem is highly nonlinear and ill-posed; therefore, reconstructed conductivity distribution suffers from low spatial resolution. The subsurface region can be approximated as piece-wise separate regions with constant conductivity in each region; therefore, the conductivity estimation problem is transformed to estimate the shape and location of the layer boundary interface. Each layer interface boundary is treated as an open boundary that is described using front points. The subsurface domain contains multi-layers with very complex configurations, and, in such situations, conventional methods such as the modified Newton Raphson method fail to provide the desired solution. Therefore, in this work, we have implemented a 7-layer artificial neural network (ANN) as an inverse problem algorithm to estimate the front points that describe the multi-layer interface boundaries. An ANN model consisting of input, output, and five fully connected hidden layers are trained for interlayer boundary reconstruction using training data that consists of pairs of voltage measurements of the subsurface domain with three-layer configuration and the corresponding front points of interface boundaries. The results from the proposed ANN model are compared with the gravitational search algorithm (GSA) for interlayer boundary estimation, and the results show that ANN is successful in estimating the layer boundaries with good accuracy.

A New Analysis of Ladder Networks by Weighted Tree (하중나무에 의한 래더 회로망의 새로운 해석 방법)

  • 이주근;이동철
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.19 no.6
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    • pp.1-8
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    • 1982
  • In this paper a new analytic method for Ladder networks by weighted tree is proposed. In contrast to conventional tree concept that represents only information structure, in this paper, a tree with hierarchical structure is established by giving wei체t of impedance Z and admittance Y to branch and representing each node of its branch as a pair of voltage and current. Then, by defining generation level from tree structure and by parsing between standand level and arbitrary level, driving point impedance, transfer function and transfer impedance are simultaneously obtained instead of complex calculation method by inspection. The validity of this method is proved by the reciprocal theorem and this method is applied to four-terminal constants and the feedback network.

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Investigation and measurement of indoor low voltage powerline impedance for high data rate powerline communications (PLC) (고속 전력선 통신용 옥내 저전압 전력선 임피던스 측정 및 특성 연구)

  • 박영진;김관호
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.41 no.8
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    • pp.93-97
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    • 2004
  • Since powerline for powerline communications (PLC) is designed for supplying electric power using 60 Hz wave, they will have different electrical behaviors for high data rate PLC whose bandwidth is allocated between 1 MHz and 30 MHz. Thus, it is necessary to investigate the different properties in this frequency bandwidth for the high data rate PLC. In this paper, low voltage (220V) powerline impedance for indoor high data rate PLC in between 1 MHz and 30 MHz is measured. For measurement a low voltage coupling unit is made and a vector network analyzer is used. A T-equivalent circuit of the low voltage coupling unit is obtained and then powerline impedance is derived by measuring the reflection coefficient of the total powerline network. With the method proposed, impedance is measured in case of a general korean apartment and its property is analyzed. Measurement shows that the average impedance is about 100Ω.

Analysis of Chip Performance by Core and I/O SSN Noise on DLL Board (DLL 보드 상에 코어 및 I/O 잡음에 의한 칩의 성능 분석)

  • Cho, Sung-Gon;Ha, Jong-Chan;Wee, Jae-Kyung
    • Journal of the Microelectronics and Packaging Society
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    • v.13 no.4
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    • pp.9-15
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    • 2006
  • This paper shows the impedance profile of PEEC(Partial Equivalent Electrical Circuit) PDN(Power Distribution Networks) including core and I/O circuit. Through the simulated results, we find that the core power noise having connection with I/O power is affected by I/O switching. Also, using designed $74{\times}5inch$ DLL(Delay Locked Loop) test board, we analyzed the effect of power noise on operation region of chip. Jitter of a DLL measure for frequency of $50{\sim}400MHz$ and compared with impedance obtained result of simulation. Jitter of a DLL are increased near about frequency of 100MHz. It is reason that the resonant peak of PDNs has an impedance of more the 1ohm on 100MHz. we present the impedance profile of a chip and board for the decoupling capacitor reduced the target impedance. Therefore, power supply network design should be considered not only decoupling capacitors but also core switching current and I/O switching current.

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Criteria and Limitations for Power Rails Merging in a Power Distribution Network Design

  • Chew, Li Wern
    • Journal of the Microelectronics and Packaging Society
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    • v.20 no.4
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    • pp.41-45
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    • 2013
  • Modern electronic devices such as tablets and smartphones are getting more powerful and efficient. The demand in feature sets, functionality and usability increase exponentially and this has posed a great challenge to the design of a power distribution network (PDN). Power rails merging is a popular option used today in a PDN design as numerous power rails are no longer feasible due to form factor limitation and cost constraint. In this paper, the criteria and limitations for power rails merging are discussed. Despite having all the advantages such as pin count reduction, decoupling capacitors sharing, lower impedance and cost saving, power rails merging can however, introduce coupling noise to the system. In view of this, a PDN design with power rails merging that fulfills design recommendations and specifications such as noise target, power well placement, voltage supply values as well as power supply quadrant assignment is extremely important.

Fault Location using Neuro-Fuzzy in Combined Transmission Lines with Underground Power Cables (뉴로-퍼지를 이용한 혼합송전계통에서의 고장점 추정)

  • Kim, Kyoung-Ho;Lee, Jong-Beom
    • Proceedings of the KIEE Conference
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    • 2002.11b
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    • pp.319-322
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    • 2002
  • Distance relay is operated in calculating line impedance. It can be worked accurately in overhead line. However, power cables or combined transmission lines need compensation for calculated impedance because cable systems have sheaths, grounding wires and sheath voltage limiters(SVLs) Neuro-fuzzy can be viewed either as a fuzay system, a neural network or fuzzy neural network and it can estimate the location of the fault accurately. In this paper, fault section and fault location can be classified and estimated in neuro- fuzzy inference system and neural network.

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