• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.4
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• pp.318-328
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• 2011

Stage-level reconfigurable chip multiprocessor (CMP) aims to achieve highly reliable and fault tolerant computing by using interwoven pipeline stages and on-chip interconnect for communicating with each other. The existing crossbar-switch based stage-level reconfigurable CMPs offer high reliability at the cost of significant area/power overheads. These overheads make realizing large CMPs prohibitive due to the area and power consumed by heavy interconnection networks. On other hand, area/power-efficient architectures offer less reliability and inefficient stage-level resource utilization. In this paper, I propose a hierarchical multiplexing interconnection structure in lieu of crossbar interconnect to design area/power-efficient stage-level reconfigurable CMP. The proposed approach is able to keep the reliability offered by the crossbar-switch while reducing the area and power overheads. Experimental results show that the proposed approach reduces area by up to 21% and power by up to 32% when compared with the crossbar-switch based interconnection network.

• ETRI Journal
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• v.41 no.5
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• pp.670-683
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• 2019

In this paper, we analyzed the signal integrity of a system interconnection module for a proposed high-density server. The proposed server integrates several components into a chassis. Therefore, the proposed server can access multiple computing resources. To support the system interconnection, among the highly integrated computing resources, the interconnection module, which is based on Serial RapidIO, has been newly adopted and supports a bandwidth of 800 Gbps while routing 160 differential signal traces. The module was designed for two different stack-up types on a printed circuit board. Each module was designed into 12- (version 1) and 14-layer (version 2) versions with thicknesses of 1.5T and 1.8T, respectively. Version 1 has a structure with two consecutive high-speed signal-layers in the middle of two power planes, whereas Version 2 has a single high-speed signal placed only in the space between two power planes. To analyze the signal integrity of the module, we probed the S-parameters, eye-diagrams, and crosstalk voltages. The results show that the high-speed signal integrity of Version 2 has a better quality than Version 1, even if the signal trace length is increased.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.37 no.9
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• pp.663-670
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• 1988

Advances in VLSI technology have made it possible to have a larger number of processing elements to be included in highly parallel processor system. A system with a large number of processing elements and memory requires a complex data path. Multistage Interconnection networks(MINS) are useful in providing programmable data path between processing elements and memory modules in multiprocessor system. In this thesis, the performance of MINS for the star network has been analyzed and compared with other networks, such as generalized shuffle network, delta network, and referenced crossbar network.

• 한국정보디스플레이학회:학술대회논문집
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• 2000.01a
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• pp.89-90
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• 2000

A new technology realizing interconnection between Plastic Film LCDs panel and a driving circuit was developed under the processing condition of low temperature and pressure with ACFs developed for Plastic Film LCDs. The conduction failure of interconnection of the two resulted from elasticity, low thermal resistance and high thermal expansion of plastic substrates. Conductive particles with elasticity similar to the plastic substrate did not damaged a ITO electrode on plastic substrates, and low temperature and pressure process also did not deform the surface of plastic substrates. As a result highly reliable interconnection with minimum contact resistance was accomplished.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.6B
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• pp.563-574
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• 2004

In this paper, we propose a new class of MIN(Multistage Interconnection Network) called Combine MIN which combines static network topology and apimic network topology. Combine U provides multiple paths at a hardware cost lower than that of MIN with unique path property. Combine MIN can be constructed suitable for localized communication by providing the shortcut path and multiple paths inside the processor-memory cluster which has frequent data communications. According to the results of analysis and simulation for performance evaluation, Combine MIN shows higher performance than MINs of the same network size in the highly localized communication Therefore, Combine MIN can be used as an attractive interconnection network for parallel applications with a localized communication pattern in shared-memory multiprocessor systems.

• Proceedings of the Korean Magnestics Society Conference
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• 2010.06a
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• pp.79-79
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• 2010

Semimetallic bismuth (Bi) has been extensively investigated over the last decade since it exhibits very intriguing transport properties due to their highly anisotropic Fermi surface, low carrier concentration, long carrier mean free path l, and small effective carrier mass $m^*$. In particular, the great interest in Bi nanowires lies in the development of nanowire fabrication methods and the opportunity for exploring novel low-dimensional phenomena as well as practical application such as thermoelectricity[1]. In this work, we introduce a self-assembled interconnection of nanostructures produced by an on-film formation of nanowires (OFF-ON) method in order to form a highly ohmic Bi nanobridge. A Bi thin film was first deposited on a thermally oxidized Si (100) substrate at a rate of $40\;{\AA}/s$ by radio frequency (RF) sputtering at 300 K. The sputter system was kept in an ultra high vacuum (UHV) of $10^{-6}$ Torr before deposition, and sputtering was performed under an Ar gas pressure of 2m Torr for 180s. For the lateral growth of Bi nanowires, we sputtered a thin Cr (or $SiO_2$) layer on top of the Bi film. The Bi thin films were subsequently put into a custom-made vacuum furnace for thermal annealing to grow Bi nanowires by the OFF-ON method. After thermal annealing, the Bi nanowires cannot be pushed out from the topside of the Bi films due to the Cr (or $SiO_2$) layer. Instead, Bi nanowires grow laterally as a mean s of releasing the compressive stress. We fabricated a self-assembled Bi nanobridge (d=192 nm) device in-situ using OFF-ON through annealing at $250^{\circ}C$ for 10hours. From I-V measurements taken on the Bi nanobridge device, contacts to the nanobridge were found highly ohmic. The quality of the Bi nanobridge was also proved by the high MR of 123% obtained from transverse MR measurements. These results manifest the possibility of self-assembled nanowire interconnection between various nanostructures for a variety of applications and provide a simple device fabrication method to investigate transport properties on nanowires without complex patterning and etching processes.

• Polymer(Korea)
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• v.26 no.6
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• pp.821-828
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• 2002

Regular and highly interconnected macroporous poly(L-lactic acid) (PLLA) scaffolds with pore size of 10∼300 ㎛ were fabricated through thermally induced phase separation of a PLLA-dioxane-water ternary system in the presence of a small amount of Pluronics. Addition of Pluronics to the ternary system raised the cloud-point temperature curve in the order of P-123< F-68< F-127. The Pluronics act as nuclei for the phase separation. This assistance is enhanced with increasing length of the hydrophilic PEO blocks in the Pluronics molecules. Liquid-liquid spinodal phase separation was induced at higher temperatures in the systems containing Pluronics because the spinodal region is raised to higher temperature. The absorption of Pluronics onto the interface stabilizes a macro scale structure and increases the interconnection of pores.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.32B no.5
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• pp.720-729
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• 1995

We proposed a XMESH(crossed-mesh) topology as a suitable interconnection for the massively parallel computer architectures, and presented performance analysis of the proposed interconnection topology. Horizontally, the XMESH has the same links as those of the toroidal mesh(TMESH) or toroid, but vertically, it has diagonal cross links instead of the vertical links. It reveals desirable interconnection characteristics for the massively parallel computers as the number of nodes increases, while retaining the same structural advantages of the TMESH such as the symmetric structure, periodic placement of subsystems, and constant degree, which are highly recommended features for VLSI/WSI implementations. Furthermore, n*k XMESH can be easily expanded without increasing the diameter as long as n.leq.k.leq.n+4. Analytical performance evaluations show that the XMESH has a shorter diameter, a shorter mean internode distance, and a higher message completion rate than the TMESH or the diagonal mesh(DMESH). To confirm these results, an optimal self-routing algorithm for the proposed topology is developed and is used to simulate the average delay, the maximum delay, and the throughput in the presence of contention. In all cases, the XMESH is shown to outperform the TMESH and the DMESH regardless of the communication load conditions or the number of nodes of the networks, and can provide an attractive alternative to those networks in implementing massively parallel computers.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.52 no.5
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• pp.250-256
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• 2003

In this papur, the STATCOM (STATic synchronous COMpensator) application for efficient operations of wind farm is described. The wind farm connected with the electric power network is one of good alternative energy sources. However, it would be also highly possible that interconnection of wind farm causes unwanted influences on distribution system operation, protection and control. This paper proposes the STATCOM application for reducing the negative effects from interconnection of wind farm with distribution networks. The simulation results show that STATCOM would be on effective and useful device to resolve the bad influences from wind farm on distribution networks and improve the operational efficiency of wind farm. In the simulation, the radial distribution network of IEEE 13 bus was modeled using PSCAD/EMTDC.

• Journal of the Microelectronics and Packaging Society
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• v.29 no.2
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• pp.33-41
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• 2022

Recent necessities of research have emerged about soft interconnection technologies for stable electric connections in flexible electronics. Mechanical failure in conventional metal solder interconnection can be solved as soft interconnections based on a small elastic modulus and a thin thickness. To enable stable electric connection while improving mechanical properties, highly conductive materials be thinned or mixed with a material that has a small elastic modulus. Representative soft interconnection technologies such as thin-film metallization, flexible conductive adhesives, and liquid metal interconnections are presented in this paper, and be focused on mechanical/electric properties improving strategies and their applications.