• The Transactions of the Korean Institute of Electrical Engineers P
• /
• v.67 no.2
• /
• pp.106-111
• /
• 2018

Recently, due to the effect of global warming, the high temperature phenomenon continues, and the time for workers exposed to high temperature, cold and infrared is increasing and then safety is threatened. Due to the nature of on-site work, the work is being carried out in an unreasonable manner due to the process, which is exposed to disasters due to high temperature and cold. Even though the injured skin may be damaged, the worker may not be aware of it and may be injured. By understanding the working environment of the worker and calculating the risk index and expressing it on the helmet, the surrounding colleagues inform the worker of the risk and take appropriate measures so that the accident can be prevented in advance. This study was conducted to investigate the effect of exposure duration on the workers' by measuring the exposure time, the risk index is displayed in the form of a traffic light to the helm, informing neighboring workers and managers, and transmitting to the workers by voice.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2002.07b
• /
• pp.805-808
• /
• 2002

A carbon monoxide gas sensor utilizing Pt-SiC, Pt-SnO2-SiC diode structure was fabricated. Since the operating temperature for silicon devices in limited to 200oC, sensor which employ the silicon substrate can not at high temperature. In this study, CO gas sensor operating at high temperature which utilize SiC semiconductor as a substrate was developed. Since the SiC is the semiconductor with wide band gap. the sensor at above $700^{\circ}C$. Carbon monoxide-sensing behavior of Pt-SiC, Pt-SnO2-SiC diode is systematically compared and analyzed as a function of carbon monoxide concentration and temperature by I-V and ${\Delta}$I-t method under steady-state and transient conditions.

• Journal of the Semiconductor & Display Technology
• /
• v.15 no.2
• /
• pp.74-80
• /
• 2016

This study presents a thermal device specially designed for thermal nanoimprint lithography equipments, which requires the capability of rapid heating and cooling, high temperature uniformity and the material strength to endure high stamping pressure. The proposal to meet these requirements is a planar-type hot plate extensible to a large area, in which long circular cartridge heaters and heat pipes are installed inside in parallel. The heat pipes are connected to the outside water cooling chamber. A hot plate made of stainless steel is fabricated with a dimension $240mm{\times}240mm{\times}20mm$. Laboratory experiments are conducted to examine the thermal performance of the hot plate. The results illustrate that the employment of heat pipes leads to a notable enhancement of temperature uniformity in the device and provides an efficient heat delivery from the hot plate to outside. It is verified that the suggested hot plate could be a feasible thermal tool for thermal nanoimprint lithography, satisfying the major design requirements.

• Journal of the Semiconductor & Display Technology
• /
• v.16 no.4
• /
• pp.91-96
• /
• 2017

In this computational study of optical fiber manufacturing, WOW (wet-on-wet) double coating process on freshly drawn glass fiber has been numerical modelled and simulated using a simplified geometry of typical optical fiber coating apparatus. The numerical domain includes primary and secondary coating dies along with secondary coating cup and the interface between primary and secondary coating liquids are investigated using level set method. Coating liquid viscosity is an important parameter and its dependence on temperature is also considered. Since there would be possibility for pressure and temperature of primary coating liquid to be increased substantially at high fiber drawing speed, the effects of increased pressure and temperature of primary coating liquid are examined on flow patterns of coating liquids in secondary coating cup. In case that both pressure and temperature of primary coating liquid are high enough, liquid interface becomes noticeably unstable and this flow instability could adversely affect the uniform coatings and final quality of produced optical fiber.

• Journal of the Semiconductor & Display Technology
• /
• v.22 no.3
• /
• pp.1-7
• /
• 2023

Recently, in the semiconductor industry, memory device market is focusing on producing ultra-thin wafers for high integration. In the wafer manufacturing process, wafers after backgrinding and CMP process must be picked up as individual dies and subjected to be peeled off from the dicing tape. However, ultra-thin dies are vulnerable to the possibility of breakage and failure in their thickness and size. This research studies the mechanism of peeling a die with a high-aspect ratio using a thermopneumatic method instead of a die ejector with physical pins. Setting compressed air and the temperature as main factors, we determine the success of the digester using thermopneumatic system and analyze the good die to find the possibility of making mass-production equipment.

• Journal of IKEEE
• /
• v.25 no.3
• /
• pp.467-472
• /
• 2021

Stable operation of semiconductor devices is needed even at high temperatures. Among the structures of semiconductor devices, the area that can cause unstable electrical responses at high temperatures is the contact layer between the metal and the semiconductor. In this study, the effect of annealing conditions included in the process of forming a contact layer of nickel silicide(NiSix) on a p-type SiC layer on the specific contact resistance of the contact layer and the total resistance between the metal and the semiconductor was investigated. To this end, a series of electrodes for TLM (transfer length method) measurements were patterned on the 4 inch p-type SiC layer under conditions of changing annealing temperature of 1700 and 1800 ℃ and annealing time of 30 and 60 minutes. As a result, it was confirmed that the annealing conditions affect the resistance of the contact layer and the electrical stability of the device.

• The Magazine of the IEIE
• /
• v.37 no.8
• /
• pp.50-59
• /
• 2010

$0.18-{\mu}m$ high voltage technology 13.5V high voltage well-based symmetric EDMOS isolated by MTI was designed and fabricated. Using calibrated process and device model parameters, the characteristics of the symmetric and asymmetric EDMOS have been simulated. The asymmetric EDMOS has higher performance, better $R_{sp}$ / BVDSS figure-of-merit, short-channel immunity and smaller pitch size than the symmetric EDMOS. The asymmetric EDMOST is a good candidate for low-power and smaller source driver chips. The low voltage logic well-based EDMOS process has advantages over high voltage well-based EDMOS in process cost by eliminating the process steps of high-voltage well/drift implant, high-temperature long-time thermal steps, etc. The specific on-resistance of our well-designed logic well-based EDMOSTs is compatible with the smallest one published. TCAD simulation and measurement results show that the improved logic well-based nEDMOS has better electrical characteristics than those of the conventional one. The improved EDMOS proposed in this paper is an excellent candidate to be integrated with low voltage logic devices for high-performance low-power low-cost chips.

• Journal of the Microelectronics and Packaging Society
• /
• v.21 no.2
• /
• pp.13-21
• /
• 2014

Technology for high power devices has made impressive progress in increasing the current density of power semiconductor, system module, and design optimization, which realize high power systems with heterogeneous functional integration. Depending on the performance development of high power semiconductor, packaging technology of high power device is urgently required for efficiency improvement of the device. Power device packaging must provide superior thermal management due to high operating temperature of power modules. Here we, therefore, review critical challenges of typical power electronics packaging today including core assembly processes, component materials, and reliability evaluation regulations.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.13 no.6
• /
• pp.622-634
• /
• 2013

The circuit level implementation of nanoscale Insulated Shallow Extension Silicon On Nothing (ISE-SON) MOSFET has been investigated and compared with the other conventional devices i.e. Insulated Shallow Extension (ISE) and Silicon On Nothing (SON) using the ATLAS 3D device simulator. It can be observed that ISE-SON based inverter shows better performance in terms of Voltage Transfer Characteristics, noise margin, switching current, inverter gain and propagation delay. The reliability issues of the various devices in terms of supply voltage, temperature and channel length variation has also been studied in the present work. Logic circuits (such as NAND and NOR gate) and ring oscillator are also implemented using different architectures to illustrate the capabilities of ISE-SON architecture for high speed logic circuits as compared to other devices. Results also illustrates that ISE-SON is much more temperature resistant than SON and ISE MOSFET. Hence, ISE-SON enables more aggressive device scaling for low-voltage applications.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.8 no.1
• /
• pp.12-16
• /
• 1983

This paper is dealing a $V_3O_5-P_2O_5$ metal oxide glass semiconductor. This semiconductor is easy to fabricate in the atmospheric condition at relatively low temperature. The element is made like a bead, and platinum segments are used as electrodes. Other kind of metal withstanding high temperature near 1000C can also be used as electrode. Experiment verifies that the fabricated element has the resistance in the order of about ~$10^5\;\Omega$, and shows negative resistance characteristics and switching characteristics with respect to temperature. An equivalent circuit of the element is proposed based on its electrical characteristcs.