• Design & Manufacturing
• /
• 제16권1호
• /
• pp.15-20
• /
• 2022

This paper is about elimination the situation in which gas sensor data becomes inaccurate due to temperature control when a semiconductor gas sensor is driven. Recently, interest in semiconductor gas sensors is high because semiconductor sensors can be driven with small and low power. Although semiconductor-type gas sensors have various advantages, there is a problem that they must operate at high temperatures. First temperature control was configured to adjust the temperature value of the heater mounted on the gas sensor. At that time, in controlling the heater temperature, gas sensor data are fluctuated despite supplying same gas concentration according to the temperature controlled. To resolve this problem, gas and temperature are extracted as a data. And then, a relation function is constructed between gas and temperature data. At this time, it is included low pass filter to get the stable data. In this paper, we can find optimal gain and parameters between gas and temperature data by using genetic algorithm.

• 반도체디스플레이기술학회지
• /
• 제9권4호
• /
• pp.71-76
• /
• 2010

According to recent changes in industry for semiconductor devices, a low-temperature treatment has become a necessity. These changes relate to size refinement and the development of new materials. While variation in cooling efficiency does not affect the yield when using a high-temperature treatment, uniform cooling efficiency is necessary avoid "inconsistencies/bends" in low temperature treatments. However it is difficult to increase temperature stabilization in low temperature treatments. In this paper, using CFD (Computer Fluid Dynamics), we analyze and manipulate the design and input of the low-temperature system to attempt to control for temperature variations within the quartz tube, of which airflow appears to be a predominant factor. This simulation includes variable inputs such as airflow rate, head pressure, and design manipulations in the S.C.U. (Super Cooling Unit).

• 전력전자학회:학술대회논문집
• /
• 전력전자학회 2015년도 전력전자학술대회 논문집
• /
• pp.159-160
• /
• 2015

Recently, it is increased to use the portable device with small size. It is also increasing for demand of a small size adapter. To reduce the size of components, switching frequency has to be increased. But it causes higher switching loss and temperature of components. Especially, the temperature of adapter must be limited because adapter can be easily touched when portable device is being charged. To reduce temperature of adapter, high efficiency is essential. To solve this problem, this paper proposes design of resonance frequency optimization for LLC converter with high efficiency and low temperature of passive components.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2000년도 하계종합학술대회 논문집(2)
• /
• pp.60-63
• /
• 2000

We have investigated the relationship between electrical and morphological properties of titanium silicide films. In this study, the C54 titanium silicides were formed by using high temperature sputtering and one-step annealing. From the measurement of electrical and morphological properties, a smooth surface and a relaxed roughness were observed for the titanium silicide film fabricated by high temperature sputtering. And it seems that the previous effect could improve electrical properties.

• 마이크로전자및패키징학회지
• /
• 제27권1호
• /
• pp.1-7
• /
• 2020

The backside metallization process is typically used to attach a chip to a lead frame for semiconductor packaging because it has excellent bond-line and good electrical and thermal conduction. In particular, the backside metal with the Ag/Sn/Ag sandwich structure has a low-temperature bonding process and high remelting temperature because the interfacial structure composed of intermetallic compounds with higher melting temperatures than pure metal layers after die attach process. Here, we introduce a die attach process with the Ag/Sn/Ag sandwich structure to apply commercial semiconductor packages. After the die attachment, we investigated the evolution of the interfacial structures and evaluated the shear strength of the Ag/Sn/Ag sandwich structure and compared to those of a commercial backside metal (Au-12Ge).

• 반도체디스플레이기술학회지
• /
• 제20권2호
• /
• pp.19-24
• /
• 2021

As the size of semiconductor devices decreases, the etching pattern becomes very narrow and a deep high aspect ratio process becomes important. The cryogenic etching process enables high aspect ratio etching by suppressing the chemical reaction of reactive ions on the sidewall while maintaining the process temperature of -100℃. ESC is an important part for temperature control in cryogenic etching equipment. Through the cooling path inside the ESC, liquid nitrogen is used as cooling water to create a cryogenic environment. And since the ESC directly contacts the wafer, it affects the temperature uniformity of the wafer. The temperature uniformity of the wafer is closely related to the yield. In this study, the cooling path was designed and analyzed so that the wafer could have a uniform temperature distribution. The optimal cooling path conditions were obtained through the analysis of the shape of the cooling path and the change in the speed of the coolant. Through this study, by designing ESC with optimal temperature uniformity, it can be expected to maximize wafer yield in mass production and further contribute to miniaturization and high performance of semiconductor devices.

• 한국전기전자재료학회논문지
• /
• 제35권1호
• /
• pp.80-85
• /
• 2022

ZnO-based transparent conductive films have been widely studied to achieve high performance optoelectronic devices such as next generation flexible and transparent display systems. In order to achieve a transparent flexible ZnO-based device, a low temperature growth technique using a flexible polymer substrate is required. In this work, high quality flexible ZnO films were grown on colorless polyimide substrate using atomic layer deposition (ALD). Transparent ZnO films grown from 80 to 200℃ were fabricated with a metal-semiconductor-metal structure photodetectors (PDs). As the growth temperature of ZnO film increases, the photocurrent of UV PDs increases, while the sensitivity of that decreases. In addition, it is found that the response times of the PDs become shorter as the growth temperature increases. Based on these results, we suggest that high-quality ZnO film can be grown below 200℃ in an atomic layer deposition system, and can be applied to transparent and flexible UV PDs with very fast response time and high photocurrent.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제17권2호
• /
• pp.265-270
• /
• 2017

4H-SiC has attracted attention for high-power and high-temperature metal-oxide-semiconductor field-effect transistors (MOSFETs) for industrial and automotive applications. The gate oxide in the 4H-SiC MOS system is important for switching operations. Above $1000^{\circ}C$, thermal oxidation initiates $SiO_2$ layer formation on SiC; this is one advantage of 4H-SiC compared with other wide band-gap materials. However, if post-deposition annealing is not applied, thermally grown $SiO_2$ on 4H-SiC is limited by high oxide charges due to carbon clusters at the $SiC/SiO_2$ interface and near-interface states in $SiO_2$; this can be resolved via low-temperature deposition. In this study, low-temperature $SiO_2$ deposition on a Si substrate was optimized for $SiO_2/4H-SiC$ MOS capacitor fabrication; oxide formation proceeded without the need for post-deposition annealing. The $SiO_2/4H-SiC$ MOS capacitor samples demonstrated stable capacitance-voltage (C-V) characteristics, low voltage hysteresis, and a high breakdown field. Optimization of the treatment process is expected to further decrease the effective oxide charge density.

• 대한전기학회논문지:전기물성ㆍ응용부문C
• /
• 제52권10호
• /
• pp.451-457
• /
• 2003

The silicon wafer is stable status at room temperature, but it is weak at high temperatures which is necessary for it to be fabricated into a power semiconductor device. During thermal diffusion processing, a high temperature produces a variety thermal stress to the wafer, resulting in device failure mode which can cause unwanted oxide charge or some defect. This disrupts the silicon crystal structure and permanently degrades the electrical and physical characteristics of the wafer. In this paper, the electrical characteristics of a single oxide layer due to high temperature diffusion process, wafer resistivity and thickness of polyback was researched. The oxide quality was examined through capacitance-voltage characteristics, defect density and BMD(Bulk Micro Defect) density. It will describe the capacitance-voltage characteristics of the single oxide layer by semiconductor process and device simulation.

• 설비공학논문집
• /
• 제22권11호
• /
• pp.760-766
• /
• 2010

Excessive heat occurs during semiconductor manufacturing process. Thus, precise control of temperature is required to maintain constant chamber-temperature and also wafer-temperature in the chamber. Compared to an industrial chiller, semiconductor chiller's power consumption is very high due to its continuous operation for a year. Considering the high power consumption, it is necessary to develop an energy efficient chiller by optimizing operation control. Therefore, in this study, a semiconductor chiller is experimentally investigated to suggest energy-saving direction by conducting load change, temperature rise and fall and control precision experiments. The experimental study shows the cooling capacity of dual-channel chiller rises over 30% comparing to the conventional chiller. The time and power consumption in the temperature rising experiment are 43 minutes and 8.4 kWh, respectively. The control precision is the same as ${\pm}1^{\circ}C$ at $0^{\circ}C$ in any cases. However, it appears that the dual channel's control precision improves to ${\pm}0.5^{\circ}C$ when the setting temperature is over $30^{\circ}C$.