• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제48권1호
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• pp.51-56
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• 1999

This paper presents a new transient overvoltage blocking device (TOBD) for info-communication facilities with low power and high frequency bandwidth. Conventional protection devices have some problems such as low frequency bandwidth, low energy capacity and high remnant voltage. In order to improve these limitations, thehybrid type TOBD, which consists of a gas tube, avalanche diodes and junction typefield effect transistors (JFETs), was designed and fabricated. The TOBD differs from the conventional protection devices in configuration, and JFETs were used as an active non-linear element and a high speed switching diode with low capacitance limits high current. Therefore the avalanche dilde with low energy capacity are protected fromthe high current, and the TOBD has a very small input capacitance. From the performance test using combination surge generator, which can produce $1.2/50\mus\;4.2kV_{max}\; 8/20\mus\; 2.1kA_{max}$, it is confirmed that proposed TOBD has an excellent protection performance in tight clamping voltage and limiting current characteristics.

• 한국전기전자재료학회논문지
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• 제28권6호
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• pp.371-374
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• 2015

This paper suggests a high performance lateral super barrier rectifier (Lateral SBR) device which has the advantages of both Schottky diode and pn junction, that is, low forward voltage and low leakage current, respectively. Advantage of the proposed lateral SBR is that it can be easily implemented and integrated in current BCD platform. As a result of simulation using TCAD, BVdss = 48 V, $V_F=0.38V$ @ $I_F=35mA$, T_j = $150^{\circ}C$ were obtained with very low leakage current characteristic of 3.25 uA.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2010년도 제39회 하계학술대회 초록집
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• pp.294-294
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• 2010

Over the last decade, dye-sensitized solar cell (DSSC) has attracted much attention due to the high solar-to-electricity conversion efficiency up to 10% as well as low cost compared with p-n junction photovoltaic devices. DSSC is composed of mesoporous TiO2 nanoparticle electrodes coated with photo-sensitized dye, the redox electrolyte and the metal counter electrode. The performances of DSSC are dependent on constituent materials and interface as well as device structure. Replacing the heavy glass substrate with plastic materials is crucial to enlarge DSSC applications for the competition with inorganic based thin film photovoltaic devices. One of the biggest problems with plastic substrates is their low-temperature tolerance, which makes sintering of the photoelectrode films impossible. Therefore, the most important step toward the low-temperature DSSC fabrication is how to enhance interparticle connection at the temperature lower than $150^{\circ}C$. In this talk, the key issues for high efficiency plastic solar cells will be discussed, and several strategies for the improvement of interconnection of nanoparticles and bendability will also be proposed.

• 한국진공학회지
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• 제6권4호
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• pp.326-336
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• 1997

트랜지스터의 소오스/드레인 접합 특성에 가장 큰 영향을 미치는 인자는 이온 주입 시 발생한 실리콘 내에 발생한 결합이라는 사실에 착안하여, 기존 소오스/드레인 접합 형성 공정과 다른 새로운 방식을 도입하여 이온 주입에 의해 생긴 결함의 제어를 통해 고품질 초 저접합 $p^+$-n접합을 형성하였다. 기존의 $p^+$소오스/드레인 접합 형성 공정은 $^{49}BF_2^+$ 이온 주입 후 층간 절연막들인 TEOS(Tetra-Ethyl-Ortho-Silicate)막과 BPSG(Boro-Phospho-Silicate-Glass)막을 증착 후 BPSG막 평탄화를 위한 furnace annealing 공정으로 진행된다. 본 연구에서는 이러한 기존 공정과는 달리 층간 절연막 증착 전 저온 RTA첨가 방법, $^{49}BF_2^+$와 $^{11}B^+$ 을 혼합하여 이온 주입하는 방법, 그리고 이온 주입 후 잔류 산화막을 제거하고 MTO(Medium temperature CVD oxide)를 증착하는 방법을 제시하 였으며, 각각의 방법은 모두 이온 주입에 의한 실리콘 내 결합 농도를 줄여 기존의 방법보 다 더 우수한 양질의 초 저접합을 형성할 수 있었다.

• 한국재료학회지
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• 제27권2호
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• pp.107-112
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• 2017

The BCBJ (Back Contact and Back Junction) or back-lit solar cell design eliminates shading loss by placing the pn junction and metal electrode contacts all on one side that faces away from the sun. However, as the electron-hole generation sites now are located very far from the pn junction, loss by minority-carrier recombination can be a significant issue. Utilizing Medici, a 2-dimensional semiconductor device simulation tool, the interdependency between the substrate thickness and the minority-carrier recombination lifetime was studied in terms of how these factors affect the solar cell power output. Qualitatively speaking, the results indicate that a very high quality substrate with a long recombination lifetime is needed to maintain the maximum power generation. The quantitative value of the recombination lifetime of minority-carriers, i.e., electrons in p-type substrates, required in the BCBJ cell is about one order of magnitude longer than that in the front-lit cell, i.e., $5{\times}10^{-4}sec$ vs. $5{\times}10^{-5}sec$. Regardless of substrate thickness up to $150{\mu}m$, the power output in the BCBJ cell stays at nearly the maximum value of about $1.8{\times}10^{-2}W{\cdot}cm^{-2}$, or $18mW{\cdot}cm^{-2}$, as long as the recombination lifetime is $5{\times}10^{-4}s$ or longer. The output power, however, declines steeply to as low as $10mW{\cdot}cm^{-2}$ when the recombination lifetime becomes significantly shorter than $5{\times}10^{-4}sec$. Substrate thinning is found to be not as effective as in the front-lit case in stemming the decline in the output power. In view of these results, for BCBJ applications, the substrate needs to be only mono-crystalline Si of very high quality. This bars the use of poly-crystalline Si, which is gaining wider acceptance in standard front-lit solar cells.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2006년도 제37회 하계학술대회 논문집 C
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• pp.1370-1371
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• 2006

An electrostatic discharge (ESD) protection device, so called, N-type extended drain silicon controlled rectifier (NEDSCR) device, was analyzed for high voltage I/O applications. A conventional NEDSCR device shows typical SCR-like characteristics with extremely low snapback holding voltage. This may cause latchup problem during normal operation. However, a modified NEDSCR device with proper junction / channel engineering demonstrates itself with both the excellent ESD protection performance and the high latchup immunity.

• 한국전자파학회논문지
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• 제16권7호
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• pp.732-739
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• 2005

본 논문에서는 E-평면 T형 분기 도파관을 갖는 Ka대역(20/30 GHz) 다이플렉서의 설계 및 구현에 관해 논하였다. 본 논문의 도파관 다이플렉서는 송신 필터 및 수신 필터를 E-평면 T형 분기 도파관으로 연결하여 E-평면으로 대칭이 되도록 하였다. T형 분기 도파관을 E-평면으로 선택한 이유는 제작시 생기는 절단면을 전류 밀도가 가장 낮은 지역에 두어 PIM(Passive Intermodulation) 레벨을 줄이기 위해서이다. 본 논문의 다이플렉서는 등가 모델을 사용하여 최적 설계를 수행함으로써 해석 시간을 줄이고자 하였다. 또한, 고전력 전송이 가능한 구조로 설계한 후 멀티팩션 해석을 수행하였으며, 해석 결과는 12 dB 마진을 확보하여 ESA/ESTEC 권고 사항을 만족함을 보였다. 제작된 다이플렉서는 전기적 성능 시험 결과를 통해 송수신 대역에서 반사 손실 22 dB 이상, 삽입 손실 0.20 dB 이하, 그리고 -40 dB 이하의 격리도 특성을 가져 요구 사항을 만족함을 보였고, 이로써 설계 결과가 검증되었다.

• 한국초전도학회:학술대회논문집
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• 한국초전도학회 1999년도 High Temperature Superconductivity Vol.IX
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• pp.185-188
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• 1999

Biepitaxial Y$_1Ba_2Cu_3O_{7-x}$ (YBCO) and La$_{0.2}Sr_{0.8}MnO_3$ (LSMO) thin films have been prepared on SrTiO$_3$ buffer layer and MgO seed layer grown on Al$_2O_3$(11${\bar{2}}$0)substrates by dc-sputtering with hollow cylindrical targets, respectively. We charaterized Josephson properties and significantly large magnetoresistance in YBCO and LSMO films with 45$^{\circ}$ grain boundary junction, respectively. The observed working voltage (I$_cR_n$) at 77 K in grain boundary junction was below 10${\mu}$V, which is typical I$_cR_n$ value of single biepitaxial Josephson junction. The field magnetoresistance ratio (MR) of LSMO grain boundary juncoon at 77K was enhanced to 13%, which it was significant MR value with high magnetic field sensitivity at a low field of 250 Oe. These results indicate that inserting the insulating layer instead of the grain boundary layer with metallic phase can be possible to apply a new SIS Josephson junction and a novel magnetic device using spin-polarized tunneling junction.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2013년도 제44회 동계 정기학술대회 초록집
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• pp.387-387
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• 2013

Currently, the flash memory and the dynamic random access memory (DRAM) have been used in a variety of applications. However, the downsizing of devices and the increasing density of recording medias are now in progress. So there are many demands for development of new semiconductor memory for next generation. Magnetic random access memory (MRAM) is one of the prospective semiconductor memories with excellent features including non-volatility, fast access time, unlimited read/write endurance, low operating voltage, and high storage density. MRAM is composed of magnetic tunnel junction (MTJ) stack and complementary metal-oxide semiconductor (CMOS). The MTJ stack consists of various magnetic materials, metals, and a tunneling barrier layer. Recently, MgO thin films have attracted a great attention as the prominent candidates for a tunneling barrier layer in the MTJ stack instead of the conventional Al2O3 films, because it has low Gibbs energy, low dielectric constant and high tunneling magnetoresistance value. For the successful etching of high density MRAM, the etching characteristics of MgO thin films as a tunneling barrier layer should be developed. In this study, the etch characteristics of MgO thin films have been investigated in various gas mixes using an inductively coupled plasma reactive ion etching (ICPRIE). The Cl2/Ar, CH3OH/Ar, and CH4/Ar gas mix were employed to find an optimized etching gas for MgO thin film etching. TiN thin films were employed as a hard mask to increase the etch selectivity. The etch rates were obtained using surface profilometer and etch profiles were observed by using the field emission scanning electron microscopy (FESEM).

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2010년도 하계학술대회 논문집
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• pp.244-244
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• 2010

Doping process of crystalline silicon solar cell process is very important which is as influential on efficiency of solar. Doping process consists of pre -deposition and diffusion. Each of these processes is important in the process temperature and process time. Through these process conditions variable, p-n junction depth can be controled to low and high. In this paper, we studied a optimized doping pre-deposition temperature for high solar cell efficiency. Using a $200{\mu}m$ thickness multi-crystalline silicon wafer, fixed conditions are texture condition, sheet resistance($50\;{\Omega}/sq$), ARC thickness(80nm), metal formation condition and edge isolation condition. The three variable conditions of pre-deposition temperature are $790^{\circ}C$, $805^{\circ}C$ and $820^{\circ}C$. In the $790^{\circ}C$ pre-deposition temperature, we achieved a best solar cell efficiency of 16.2%. Through this experiment result, we find a high efficiency condition in a low pre-deposition temperature than the high pre-deposition temperature. We optimized a pre-deposition temperature for high solar cell efficiency.