• 전력전자학회논문지
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• 제20권4호
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• pp.337-343
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• 2015

The multi-level inverters are highly efficient for high-power and medium-voltage AC driving applications, such as high-speed railway systems and renewable energy resources, because such inverters generate lower total harmonic distortion (THD) and electromagnetic interface (EMI). Lower switching stress occurs on switching devices compared with conventional two-level inverters. Depending on the multi-level inverter topology, the required components and number of switching devices are different, influencing the overall efficiency. Comparative studies of multi-level inverters based on loss analysis and output characteristic are necessary to apply multi-level inverters in high-power AC conversion systems. This paper proposes a theoretical loss analysis method based on piecewise linearization of characteristic curves of power semiconductor devices as well as loss analysis and output performance comparison of five-level neutral-point clamped, flying capacitor inverters, and high-level cascaded H-bridge multi-level inverters.

• 전자공학회논문지
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• 제52권10호
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• pp.56-63
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• 2015

SoC (System-on-Chip) 설계초기 상위수준에서 성능뿐만 아니라 전력 분석이 중요하다. 본 논문에서는 상위수준에서 전력 분석 정확도가 높은 클럭 게이팅 구동 신호 기반 전력 모델을 제안한다. 클럭 게이팅 구동 신호의 조합으로 전력 상태를 정의하며, 클럭 게이팅 구동 신호를 자동으로 추출하여 전력 모델을 자동으로 생성할 수 있다. 실험 결과 평균 96% 이상의 정확도를 보였으며, 상위수준에서의 전력 분석 속도는 게이트 수준 대비 평균 280배 빠른 속도향상을 보였다.

• 대한원격탐사학회지
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• 제37권1호
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• pp.97-110
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• 2021

Fog can cause large-scale human and economic damages, including traffic systems and agriculture. So, Korea Meteorological Administration is operating about 290 visibility meters to improve the observation level of fog. However, it is still insufficient to detect very localized fog. In this study, high-resolution grid-type visibility data were retrieved from irregularly distributed visibility data across the country. To this end, three objective analysis techniques (Inverse Distance Weighting (IDW), Ordinary Kriging (OK) and Universal Kriging (UK)) were used. To find the best method and parameters, sensitivity test was performed for the effective radius, power parameter and variogram model that affect the level of objective analysis. Also, the effect of data distribution characteristics (level of normality) on the performance level of objective analysis was evaluated. IDW showed a relatively high level of objective analysis in terms of bias, RMSE and correlation, and the performance is inversely proportional to the effective radius and power parameter. However, the two Krigings showed relatively low level of objective analysis, in particular, greatly weakened the variability of the variables, although the level of output was different depending on the variogram model used. As the level of objective analysis is greatly influenced by the distribution characteristics of data, power, and models used, care should be taken when selecting objective analysis techniques and parameters.

• 전력전자학회논문지
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• 제23권3호
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• pp.153-160
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• 2018

Recent trends in high-power-density applications have highlighted the importance of designing power converters with high-frequency operation. However, conventional LLC resonant converters present limitations in terms of high-frequency driving due to switching losses during the turn-off period. Switching losses are caused by the overlap of the voltage and current during this period, and can be decreased by reducing the switch voltage. In turn, the switch voltage can be reduced through a series connection of four switches, and additional circuitry is essential for balancing the voltage of each switch. In this work, a three-level LLC resonant converter that can operate at high frequency is proposed by reducing switch losses and balancing the voltages of all switches with only one capacitor. The voltage-balancing principle of the proposed circuit can be extended to n-level converters, which further reduces the switch voltage stress. As a result, the proposed circuit is applicable to high-input applications. To confirm the validity of the proposed circuit, theoretical analysis and experimental verification results from a 350 W-rated prototype are presented.

• Journal of Power Electronics
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• 제15권5호
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• pp.1380-1391
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• 2015

This paper provides a loss analysis and comparison of high power semiconductor devices in 5MW Permanent Magnet Synchronous Generator (PMSG) Medium Voltage (MV) Wind Turbine Systems (WTSs). High power semiconductor devices of the press-pack type IGCT, module type IGBT, press-pack type IGBT, and press-pack type IEGT of both 4.5kV and 6.5kV are considered in this paper. Benchmarking is performed based on the back-to-back type 3-level Neutral Point Clamped Voltage Source Converters (3L-NPC VSCs) supplied from a grid voltage of 4160V. The feasible number of semiconductor devices in parallel is designed through a loss analysis considering both the conduction and switching losses under the operating conditions of 5MW PMSG wind turbines, particularly for application in offshore wind farms. This paper investigates the loss analysis and thermal performance of 5MW 3L-NPC wind power inverters under the operating conditions of various power factors. The loss analysis and thermal analysis are confirmed through PLECS Blockset simulations with Matlab Simulink. The comparison results show that the press-pack type IGCT has the highest efficiency including the snubber loss factor.

• Journal of Electrical Engineering and information Science
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• 제2권3호
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• pp.123-131
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• 1997

Design of single stage AC/DC converter with high power factor for low power level applications is proposed. The proposed converter gives the good power factor correction, low line current harmonic distortions, and tight output voltage regulations. This converter also has a high efficiency by employing an active clamp method and synchronous rectifiers. To verify the performances of the proposed converter, a 90W-converter has been designed. The modelling of this proposed converter is power formed using an averaging technique and based on this model a detailed analysis is carried out. This prototype meets the IEC555-2 requirements satisfactorily with nearly unity power factor and high efficiency.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 추계종합학술대회 논문집(2)
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• pp.188-191
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• 2000

This paper presents a register scheduling and allocation algorithm for high level synthesis. The proposed algorithm executes the low power scheduling to reduce the switching activity using shut down technique which was not unnecessary the calculation through the extraction DFG from VHDL description. Also, the register allocation algorithm determines the minimum register after the life time analysis of all variable. It is minimum the switching activity using graph coloring technique for low power consumption. The proposed algorithm proves the effect through various filter benchmark to adopt a new scheduling and allocation algorithm considering the low power.

• 융합신호처리학회 학술대회논문집
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• 한국신호처리시스템학회 2001년도 하계 학술대회 논문집(KISPS SUMMER CONFERENCE 2001
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• pp.69-72
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• 2001

High-level synthesis는 주어진 동작과 면적, 성능, 전력 소모, 패키징, 테스팅 등의 주어진 제한을 만족하게 구현된 구조적 디자인을 생성한다. 즉 high-level syntehesis란 디지털 시스템의 알고리즘 레벨 서술로부터 레지스터 전달구조의 구현에 이르는 과정을 의미한다. 이러한 high-level synthesis의 과정은 컴파일, 분할, 스케줄링 등의 단계를 거쳐 디지털 시스템을 설계할 수 있다. 본 논문에서는 high-level synthesis의 단계중 분할 과정을 연구하고, 분할 알고리즘 중에서 min-cut 알고리즘과 simulated annealing 알고리즘을 사용하여 비교 분석하였다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권3호
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• pp.300-311
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• 2016

The analog-to-digital-converter-based (ADC-based) backplane receivers that consist of a front-end ADC followed by a digital equalizer are gaining more popularity in recent years, as they support more sophisticated equalization required for high data rates, scale better with fabrication technology, and are more immune to PVT variations. Unfortunately, designing an ADC-based receiver that meets tight power and performance budgets of high-speed backplane link systems is non-trivial as both front-end ADC and digital equalizer can be power consuming and complex when running at high speed. This paper reviews the state of art designs for the front-end ADC and digital equalizers to suggest implementation choices that can achieve high speed while maintaining low power consumption and complexity. Design-space exploration using system-level models of the ADC-based receiver allows through analysis on the impact of design parameters, providing useful information in optimizing the power and performance of the receiver at the early stage of design. The system-level simulation results with newer device parameters reveal that, although the power consumption of the ADC-based receiver may not comparable to the receivers with analog equalizers yet, they will become more attractive as the fabrication technology continues to scale as power consumption of digital equalizer scales well with process.

• Nuclear Engineering and Technology
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• 제49권2호
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• pp.426-433
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• 2017

This paper describes the development process, the innovative techniques used and insights gained from the latest integrated, full scope, multistate Level 2 PSA analysis conducted at the Leibstadt Nuclear Power Plant (KKL), Switzerland. KKL is a modern single-unit General Electric Boiling Water Reactor (BWR/6) with Mark III Containment, and a power output of $3600MW_{th}/1200MW_e$, the highest among the five operating reactors in Switzerland. A Level 2 Probabilistic Safety Assessment (PSA) analyses accident phenomena in nuclear power plants, identifies ways in which radioactive releases from plants can occur and estimates release pathways, magnitude and frequency. This paper attempts to give an overview of the advanced modeling techniques that have been developed and implemented for the recent KKL Level 2 PSA update, with the aim of systematizing the analysis and modeling processes, as well as complying with the relatively prescriptive Swiss requirements for PSA. The analysis provides significant insights into the absolute and relative importances of risk contributors and accident prevention and mitigation measures. Thanks to several newly developed techniques and an integrated approach, the KKL Level 2 PSA report exhibits a high degree of reviewability and maintainability, and transparently highlights the most important risk contributors to Large Early Release Frequency (LERF) with respect to initiating events, components, operator actions or seismic component failure probabilities (fragilities).