• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.11a
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• pp.287-288
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• 2005

In this study, we have investigated electro-optical characteristics of thermal and UV stressed TN cells on the rubbed polyimide surface. Mono-domain alignments of thermal stressed TN cells over temperature of liquid crystal isotropic phase were almost same that of no thermal stressed TN cells. Also, threshold voltage and response time of thermal stressed TN cells were same that of no thermal stressed TN cells. Finally, the residual DC voltage of the thermal stressed TN cell on the polyimide surface show decrease of characteristics as increasing thermal stress time. Therefore, thermal stability of TN cell was decreased by high thermal stress for the long times.

• Transactions on Electrical and Electronic Materials
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• v.10 no.1
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• pp.5-8
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• 2009

The reliability of multilayer ceramic capacitor with active thin dielectric layer was investigated by highly accelerated life test at various stress condition. The distribution of multilayer ceramic capacitor failure times is plotted as a function of time from Weibull distribution function. According to the test result, voltage acceleration factor is obtained from 2.24 to 2.96. The acceleration by temperature is much higher than other values of active thick dielectric layer. It is clear that median time to failure is affected by the stress voltage for high volumetric efficiency ceramic capacitors with active thin dielectric layer. The degradation under stress of voltage involves electromigration and accumulation of oxygen vacancy at Ni electrode interface of cathode.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.145-148
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• 2001

In this paper, polycrystalline silicon thin film transistor using by Solid Phase Crystallization(SPC) were fabricated, and these devices were measured and analyzed the electrical output and transfer characteristics along to DC voltage stress. The transfer characteristics of polycrystalline silicon thin film transistor depended on drain and gate voltages. Threshold voltage is high with long channel length and narrow channel width. And output characteristics of polycrystalline silicon thin film transistor flowed abruptly much higher drain current. The devices induced electrical stress are decreased drain current. At last, field effect mobility is the faster as channel length is high and channel width is narrow.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.24 no.12
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• pp.939-943
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• 2011

In this paper, reliability of the two sandwiched MIM capacitors of $Al_2O_3-HfO_2-Al_2O_3$ (AHA) and $SiO_2-HfO_2-SiO_2$ (SHS) with hafnium-based dielectrics was analyzed using two kinds of voltage stress; DC and AC voltage stresses. Two MIM capacitors have high capacitance density (8.1 fF/${\mu}m^2$ and 5.2 fF/${\mu}m^2$) over the entire frequency range and low leakage current density of ~1 nA/$cm^2$ at room temperature and 1 V. The charge trapping in the dielectric shows that the relative variation of capacitance (${\Delta}C/C_0$) increases and the variation of voltage linearity (${\alpha}$/${\alpha}_0$) gradually decreases with stress-time under two types of voltage stress. It is also shown that DC voltage stress induced greater variation of capacitance density and voltage linearity than AC voltage stress.

• Journal of Electrical Engineering and Technology
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• v.11 no.6
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• pp.1656-1663
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• 2016

A capacitive wireless power transfer (C-WPT) system uses an electric field to transmit power through a physical isolation barrier which forms a pair of ac link capacitors between the metal plates. However, the physical dimension and low dielectric constant of the interface medium severely limit the effective link capacitance to a level comparable to the main switch output capacitance of the transmitting circuit, which thus narrows the soft-switching range in the light load condition. Moreover, by fundamental limit analysis, it can be proved that such a low link capacitance increases operating frequency and capacitor voltage stress in the full load condition. In order to handle these problems, this paper investigates optimal design of double matching transformer networks for C-WPT. Using mathematical analysis with fundamental harmonic approximation, a design guideline is presented to avoid unnecessarily high frequency operation, to suppress the voltage stress on the link capacitors, and to achieve wide ZVS range even with low link capacitance. Simulation and hardware implementation are performed on a 5-W prototype system equipped with a 256-pF link capacitance and a 200-pF switch output capacitance. Results show that the proposed scheme ensures zero-voltage-switching from full load to 10% load, and the switching frequency and the link capacitor voltage stress are kept below 250 kHz and 452 V, respectively, in the full load condition.

• Proceedings of the KIEE Conference
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• 2004.11b
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• pp.63-65
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• 2004

The recent advancement in the power electronic technique has increased the use of induction motor fed by inverter using high-frequency switching devices. Also the tendency is toward larger size and higher voltage. Therefore, The IGBT (Insulated-Gate Bipolar Transistor) that is high switching frequency element has been using increase. But, The switching surge voltage was occurred by high switching frequency of inverter has appeared a voltage doubling in the motor input terminal due to mismatching of cable characteristic impedance and motor characteristic impedance. Actually, The Switching surge voltage became the major cause to occur the insulation failure by serious voltage stress in the stator winding of induction motor. The short during rise time of switching surge and cable length is increased, the maximum transient voltage seen at the motor terminals increases. In this paper, Analyzed switching surge transient voltage of power cable pulling is used EMTP(Electromagnetic Transient Program) at the induction motor terminal and in cable.

• Journal of Electrical Engineering and Technology
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• v.7 no.5
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• pp.714-723
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• 2012

A new Z-source inverter (ZSI) topology is developed to improve voltage boost ability. The proposed topology is modified from the switched inductor topology by adding some more inductors and diodes into inductor branch to the conventional Z-source network. The modulation methods developed for the conventional ZSI can be easily utilized in the proposed ZSI. The proposed ZSI has an ability to obtain a higher voltage boost ratio compared with the conventional ZSI under the same shoot-through duty ratio. Since a smaller shoot-through duty ratio is required for high voltage boost, the proposed ZSI is able to reduce the voltage stress on Z-source capacitor and inverter-bridge. Theoretical analysis and operating principle of the proposed topology are explicitly described. In addition, the design guideline of the proposed Z-source network as well as the PWM control method to achieve the desired voltage boost factor is also analyzed in detail. The improved performances are validated by both simulation and experiment.

• Journal of Power Electronics
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• v.15 no.1
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• pp.235-245
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• 2015

This paper proposes a reactive current assignment and control strategy for a doubly-fed induction generator (DFIG) based wind-turbine generation system under generic grid voltage sag or swell conditions. The system's active and reactive power constrains during grid faults are investigated with both the grid- and rotor-side convertors (GSC and RSC) maximum ampere limits considered. To meet the latest grid codes, especially the low- and high-voltage ride-through (LVRT and HVRT) requirements, an adaptive reactive current control scheme is investigated. In addition, a torque-oscillation suppression technique is designed to reduce the mechanism stress on turbine systems caused by intensive voltage variations. Simulation and experiment studies demonstrate the feasibility and effectiveness of the proposed control scheme to enhance the fault ride-through (FRT) capability of DFIG-based wind turbines during violent changes in grid voltage.

• The Transactions of the Korean Institute of Power Electronics
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• v.18 no.4
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• pp.342-348
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• 2013

In this paper, an improved non-isolated 3-level high step-up boost converter is proposed. By using the well known duality principle, the proposed converter is derived from two-phase buck converter. Compared with the traditional boost converter and 3-level boost converter, the proposed converter can obtain very high voltage conversion ratio and the voltage stress of switching devices and diodes is only 1/4 of the output voltage. A 1 kW prototype converter is built and tested to verify performances of the proposed converter.

• Proceedings of the KIPE Conference
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• 2008.06a
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• pp.400-402
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• 2008

A new interleaved forward converter, adopting series-input parallel-output structure with a common transformer reset circuit, is proposed in this paper. Series-input structure distributes the voltage stress on switches, which makes it suitable for high input voltage application. Paralleling output stage with an interleaving technique enables the circuit handle large output current and reduces filter size. In addition, since two forward converters share one active-clamp circuit for the transformer reset, its primary structure is simplified. All these features make the proposed converter promising for high input voltage applications with high efficiency and simple structure.