• Title/Summary/Keyword: high power amplifier

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Pulsed-Bias Pulsed-RF Passive Load-Pull Measurement of an X-Band GaN HEMT Bare-chip (X-대역 GaN HEMT Bare-Chip 펄스-전압 펄스-RF 수동 로드-풀 측정)

  • Shin, Suk-Woo;Kim, Hyoung-Jong;Choi, Gil-Wong;Choi, Jin-Joo;Lim, Byeong-Ok;Lee, Bok-Hyung
    • The Journal of The Korea Institute of Intelligent Transport Systems
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    • v.10 no.1
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    • pp.42-48
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    • 2011
  • In this paper, a passive load-pull using a GaN HEMT (Gallium Nitride High Electron Mobility Transistor) bare-chip in X-band is presented. To obtain operation conditions that characteristic change by self-heating was minimized, pulsed drain bias voltage and pulsed-RF signal is employed. An accuracy impedance matching circuits considered parasitic components such as wire-bonding effect at the boundary of the drain is accomplished through the use of a electro-magnetic simulation and a circuit simulation. The microstrip line length-tunable matching circuit is employed to adjust the impedance. The measured maximum output power and drain efficiency of the pulsed load-pull are 42.46 dBm and 58.7%, respectively, across the 8.5-9.2 GHz band.

Widely-tunable high-speed wavelength converter based on four-wave mixing in a semiconductor-fiber ring laser (고리형 반도체-광섬유 레이저에서 4광파 혼합에 의한 광대역 및 고속 파장 변환기)

  • Choi, kyoung-Sun;Seo, Dong-Sun;Lee, Yoo-Seung;Ki, Ho-Jin;Jhon, Young-Min;Lee, Seok;Kim, Dong-Hwan
    • Korean Journal of Optics and Photonics
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    • v.13 no.1
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    • pp.15-20
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    • 2002
  • We demonstrate a widely-tunable wavelength converter based on four-wave mixing in a semiconductor-fiber ring laser with no external pump light. Applying 10 GHz short pulses at -8 dBm as a probe signal, we achieve continuous wavelength tuning over the semiconductor optical amplifier gain-bandwidth reaching 30 nm down- and 17 m up-wavelength conversion. In addition to the wide tuning capability, the converter shows high-speed conversion and low saturation power capabilities.

PERFORMANCE TEST FOR A PDS MICRODENSITOMETER MODEL 1010GMS

  • Hong, S.S.;Paek, W.G.;Lee, S.G.
    • Journal of The Korean Astronomical Society
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    • v.25 no.1
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    • pp.23-46
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    • 1992
  • The electrical, mechanical and optical capabilities have been tested of the microdensitometer PDS 1010GMS at the Korea Astronomy Observatory. The highest stage of scan speed 255 csu (conventional speed unit) is measured to be 47 mm/s. At this speed the position is displaced by $4{\mu}m$ to the direction of scanning and the density is underestimated by $0.4{\sim}0.7D$. Standard deviation in the measured density is proportional to $A^{-0.46}$, where A is the area of scan aperture. The accuracy of position repeatability is ${\pm}1{\mu}m$, and that of density repeatability is ${\pm}(0.003{\sim}0.03)D$. Callier coefficient is determined to be 1.37; the semispecular density is directly proportional to the diffuse density up to 3.5D. Because the logarithmic amplifier has a finite response time, the densities measured at high scan speeds are underestimated to the degree that speeds higher than 200 csu are inadequate for making an accurate astronomical photometry. After power is on, an about 5 hour period of warming is required to stabilize the system electrically and mechanically as well. On the basis of this performance test, we have determined the followings as the optimum scan parameters for the astronomical photometry: For the scan aperture $10\;\sim\;20{\mu}m$ is optimal, and for the scan speed. $20\;{\sim}\;50$ csu is appropriate. These parameter values are chosen in such a way that they may keep the density repeatability within ${\pm}0.01D$, the position displacement under $1{\mu}m$, and the density underestimation below 0.1D even in high density regions.

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A High-Speed CMOS A/D Converter Using an Acquistition-Time Minimization Technique) (정착시간 최소화 기법을 적용한 고속 CMOS A/D 변환기 설계)

  • 전병열;전영득;이승훈
    • Journal of the Korean Institute of Telematics and Electronics C
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    • v.36C no.5
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    • pp.57-66
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    • 1999
  • This paper describes a 12b, 50 Msample/s CMOS AID converter using an acquisition-time minimization technique for the high-speed sampling rate of 50 MHz level. The proposed ADC is implemented in a $0.35\mu\textrm{m}$ double-poly five-metal n-well CMOS technology and adopts a typical multi-step pipelined architecture to optimize sampling rate, resolution, and chip area. The speed limitation of conventional pipelined ADCs comes from the finite bandwidth and resulting speed of residue amplifiers. The proposed acquisition-time minimization technique reduces the acquisition time of residue amplifiers and makes the waveform of amplifier outputs smooth by controlling the operating current of residue amplifiers. The simulated power consumption of the proposed ADC is 197 mW at 3 V with a 50 MHz sampling rate. The chip size including pads is $3.2mm\times3.6mm$.

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Preliminary Research of CZT Based PET System Development in KAERI

  • Jo, Woo Jin;Jeong, Manhee;Kim, Han Soo;Kim, Sang Yeol;Ha, Jang Ho
    • Journal of Radiation Protection and Research
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    • v.41 no.2
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    • pp.81-86
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    • 2016
  • Background: For positron emission tomography (PET) application, cadmium zinc telluride (CZT) has been investigated by several institutes to replace detectors from a conventional system using photomultipliers or Silicon-photomultipliers (SiPMs). The spatial and energy resolution in using CZT can be superior to current scintillator-based state-of-the-art PET detectors. CZT has been under development for several years at the Korea Atomic Energy Research Institute (KAERI) to provide a high performance gamma ray detection, which needs a single crystallinity, a good uniformity, a high stopping power, and a wide band gap. Materials and Methods: Before applying our own grown CZT detectors in the prototype PET system, we investigated preliminary research with a developed discrete type data acquisition (DAQ) system for coincident events at 128 anode pixels and two common cathodes of two CZT detectors from Redlen. Each detector has a $19.4{\times}19.4{\times}6mm^3$ volume size with a 2.2 mm anode pixel pitch. Discrete amplifiers consist of a preamplifier with a gain of $8mV{\cdot}fC^{-1}$ and noise of 55 equivalent noise charge (ENC), a $CR-RC^4$ shaping amplifier with a $5{\mu}s$ peak time, and an analog-to-digital converter (ADC) driver. The DAQ system has 65 mega-sample per second flash ADC, a self and external trigger, and a USB 3.0 interface. Results and Discussion: Characteristics such as the current-to-voltage curve, energy resolution, and electron mobility life-time products for CZT detectors are investigated. In addition, preliminary results of gamma ray imaging using 511 keV of a $^{22}Na$ gamma ray source were obtained. Conclusion: In this study, the DAQ system with a CZT radiation sensor was successfully developed and a PET image was acquired by two sets of the developed DAQ system.

A RF MEMS Transmitter Based on Flexible Printed Circuit Boards (연성 인쇄 회로 기판을 이용한 초고주파 MEMS 송신기 연구)

  • Myoung, Seong-Sik;Kim, Seon-Il;Jung, Joo-Yong;Yook, Jong-Gwan
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.19 no.1
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    • pp.61-70
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    • 2008
  • This paper presents the flexible MEMS transmitter based on flexible printed circuit board or FPCB, which can be transformed to arbitrary shape. The FPCB is suitable to fabricate light weight and small size modules with the help of its thin thickness. Moreover a module based on FPCB can be attached on the arbitrary curved surface due to its flexible enough to be lolled up like paper. In this paper, the flexible MEMS transmitter integrated on FPCB for a short-distance sensor network which is based on orthogonal frequency division multiplexing(OFDM) communication system is proposed. The active device of the proposed flexible MEMS transmitter is fabricated on InGaP/GaAs HBT process which has been used for power amplifier design to take advantages of high linear and high efficient characteristics. Moreover, the passive devices such as the filter and signal lines are integrated and fabricated on the FPCB board. The performance of the fabricated flexible MEMS transmitter is analyzed with EVM characteristics of the output signal.

Low-voltage high-linear bipolar OTA and its application to IF bandpass Filter (저전압 고선형 바이폴라 OTA와 이를 이용한 IF 대역통과 필터)

  • Chung, Won-Sup;Son, Sang-Hee
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.44 no.7 s.361
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    • pp.37-44
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    • 2007
  • A low-voltage high-linear bipolar OTA and its application to IF bandpass filter for GSM cellular telephone are presented. The OTA consists of a low-voltage linear transconductor, a translinear current gain cell, and three current mirrors. The bandpass filter is composed of two cascaded identical second-order bandpass filters, which consist of a resistor, a capacitor, and a grounded simulated inductor realized with two OTA's and a grounded capacitor. SPICE simulations using an 8 GHz bipolar transistor-array parameter show that the OTA with a transconductance of 1 mS exhibits a linearity error of less than ${\pm}2%$ over an input voltage range of ${\pm}0.65\;V$ at supply voltages of ${\pm}2.0\;V$. Temperature coefficient of the transconductance is less than $-90ppm/^{\circ}C$. The bandpass filter has a center frequency of 85 MHz and Q-factor of 80. Temperature coefficient of the center frequency is less than $-182ppm/^{\circ}C$. The power dissipation of the filter is 128 mW.

A Design of Pipelined Analog-to-Digital Converter with Multi SHA Structure (Multi SHA 구조의 파이프라인 아날로그-디지털 변환기 설계)

  • Lee, Seung-Woo;Ra, Yoo-Chan;Shin, Hong-Kyu
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.30 no.2A
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    • pp.114-121
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    • 2005
  • In this paper, Pipelined A/D converter with multi SHA structure is proposed for high speed operation. The proposed structure incorporates a multi SHA block that consists of multiple SHAs of identical characteristics in parallel to improve the conversion speed. The designed multi SHA is operated by non-overlapping clocks and the sampling speed can be improved by increasing the number of multiplexed SHAs. Pipelined A/D converter, applying the proposed structure, is designed to satisfy requirement of analog front-end of VDSL modem. The measured INL and DNL of designed A/D converter are $0.52LSB{\sim}-0.50LSB\;and\;0.80LSB{\sim}-0.76LSB$, respectively. It satisfies the design specifications for VDSL modems. The simulated SNR is about 66dB which corresponds to a 10.7 bit resolution. The power consumption is 24.32mW.

Design of Ultra Wide Band Radar Transceiver for Foliage Penetration (수풀투과를 위한 초 광대역 레이더의 송수신기 설계)

  • Park, Gyu-Churl;Sun, Sun-Gu;Cho, Byung-Lae;Lee, Jung-Soo;Ha, Jong-Soo
    • Journal of Satellite, Information and Communications
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    • v.7 no.1
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    • pp.75-81
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    • 2012
  • This study is to design the transmitter and receiver of short range UWB(Ultra Wide Band) imaging radar that is able to display high resolution radar image for front area of a UGV(Unmanned Ground Vehicle). This radar can help a UGV to navigate autonomously as it detects and avoids obstacles through foliage. The transmitter needs two transmitters to improve the azimuth resolution. Multi-channel receivers are required to synthesize radar image. Transmitter consists of high power amplifier, channel selection switch, and waveform generator. Receiver is composed of sixteen channel receivers, receiver channel converter, and frequency down converter, Before manufacturing it, the proposed architecture of transceiver is proved by modeling and simulation using several parameters. Then, it was manufactured by using industrial RF(Radio Frequency) components and all other measured parameters in the specification were satisfied as well.

A 14b 200KS/s $0.87mm^2$ 1.2mW 0.18um CMOS Algorithmic A/D Converter (14b 200KS/s $0.87mm^2$ 1.2mW 0.18um CMOS 알고리즈믹 A/D 변환기)

  • Park, Yong-Hyun;Lee, Kyung-Hoon;Choi, Hee-Cheol;Lee, Seung-Hoon
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.43 no.12 s.354
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    • pp.65-73
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    • 2006
  • This work presents a 14b 200KS/s $0.87mm^2$ 1.2mW 0.18um CMOS algorithmic A/D converter (ADC) for intelligent sensors control systems, battery-powered system applications simultaneously requiring high resolution, low power, and small area. The proposed algorithmic ADC not using a conventional sample-and-hold amplifier employs efficient switched-bias power-reduction techniques in analog circuits, a clock selective sampling-capacitor switching in the multiplying D/A converter, and ultra low-power on-chip current and voltage references to optimize sampling rate, resolution, power consumption, and chip area. The prototype ADC implemented in a 0.18um 1P6M CMOS process shows a measured DNL and INL of maximum 0.98LSB and 15.72LSB, respectively. The ADC demonstrates a maximum SNDR and SFDR of 54dB and 69dB, respectively, and a power consumption of 1.2mW at 200KS/s and 1.8V. The occupied active die area is $0.87mm^2$.