• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2001.11b
• /
• pp.189-192
• /
• 2001

Recently, STI process is getting attention as a necessary technology for making high density of semiconductor by devices isolation method. However, it does have various problems caused by CMP nprocess, such as torn oxide defects, nitride residues on oxide, damages of si active region, contaminations due to post-CMP cleaning, difficulty of accurate end point detection in CMP process, etc. In this work, the various defects induced by CMP process was introduced and the above mentioned problems of CMP process was examined in detail. Finally, the guideline of future CMP process was presented to reduce the effects of these defects.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2001.11a
• /
• pp.189-192
• /
• 2001

Recently, STI process is getting attention as a necessary technology for making high density of semiconductor by devices isolation method. However, it does have various problems caused by CMP process, such as torn oxide defects, nitride residues on oxide, damages of si active region, contaminations due to post-CMP cleaning, difficulty of accurate end point detection in CMP process, etc. In this work, the various defects induced by CMP process was introduced and the above mentioned Problems of CMP process was examined in detail. Finally, the guideline of future CMP process was presented to reduce the effects of these defects.

• Electrical & Electronic Materials
• /
• v.8 no.5
• /
• pp.640-647
• /
• 1995

In this study, the BaTiO$\sub$3/ capacitor add to MnO$\sub$2/ like depressor and shifter were investigated for temperature or voltage compensation by structural and electrical analysis. The relative density of BCTM, generating poly crystall and formation of lattice defect, has a 90[%] over as the CaTiO$\sub$3/ come out to control grain size. The current density of BCTM2 increased non-ohmic in high-electric field but that BCTM3 and BCTM4 had a few changing. The BCTM3 and BCTM4 unformated grain boundary shown temperature compensation properties, so that the dielectric constant was low value. The curie point was near 140[.deg. C] in BCTM1 and BCTM4, but BCTM3 and BCTM4 not shown the curie point. It is found that the charging energy of BCTM4 was changed 6[%] according to rising temperature from room temperature to 417[K]. The formation of BaMnO$\sub$3/ was low dielectric constant to change frequency and temperature.

• Journal of the Korean Vacuum Society
• /
• v.1 no.1
• /
• pp.190-197
• /
• 1992

In this study we have investigated physical and electrical properties of high temperature oxide (HTO) thin film using dichlorosilane (DCS) gas. This film had low etch rate and excellent step coverage, and its characteristics of Si-O bond were similar to those of thermal oxide. I-V curves also showed similar electrical properties to those of thermally grown oxide (SiO2) while time dependent dielectric breakdown (TDDB) results revealed 1/4 value of thermal oxide. However, defect density was measured to be much lower value than that of thermal oxide.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.11 no.9
• /
• pp.705-710
• /
• 1998

Intrinsic gettering is usually to improve wafer quality, which is an important factor for reliable ULSI devices. In order to generate oxygen precipitation in lightly and heavily boron doped silicon wafers with or without high $^75 As^+$ ion implantation, the 2-step annealing method was adopted. After annealing, the were cleaved and etched with th Wright etchant. The morphology of cross section on samples was inspected by FESEM(field emission scanning electron microscopy). The morphology of unimplanted samples was rater rough than that of the implanted. Oxygen precipitation density observed by an optical microscope in lightly boron doped samples was about 3$\times10^6/cm^3$. However, in heavily boron doped samples, the density of oxygen precipitation was largest at $600^{\circ}C$ in 1st annealing, and decreased abruptly until $800^{\circ}C$, But it increased slightly at $1000^{\circ}C$ and was independent with the implantation.

• Journal of the Korean Crystal Growth and Crystal Technology
• /
• v.8 no.1
• /
• pp.29-35
• /
• 1998

Substrates, SiC raw materials and graphite crucibles were purified for growing the high quality 6H-SiC single crystal ingot. Especially, XRD data of raw materials were analyzed before and after purification. We have grown 6H-SiC single crystal ingot up to 33 mm in diameter and 11 mm in length and SiC wafer for using the substrate and observing the internal defects was about 33 mm in diameter and 0.5 mm in thickness. Utilizing optical microscpe and Raman spectroscopy, internal defects density and crystallinity of the SiC wafer obtained by purification processes before crystal growth were measured. As a result, micropipe density and planar defect density were 100/$\textrm{cm}^2$ and 30/$\textrm{cm}^2$ respectively. Therefore, high quality 6H-SiC single crystal could be grown because internal defects density of 6H-SiC single crystal ingot was decreased by the purification processes before crystal growth.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.34 no.4
• /
• pp.246-250
• /
• 2021

TFTs technologies with as high mobility as possible is essential for high-performance large displays. TFTs using nanocrystalline silicon thin films can achieve higher mobility. In this work, the change of the crystalline volume fraction at different hydrogen dilution ratios was investigated by depositing nc-Si:H thin films using PECVD. It was observed that increasing hydrogen dilution ratio increased not only the crystalline volume fraction but also the crystallite size. The thin films with a high crystalline volume fraction (55%) and a low defect density (10¹⁷ cm^-3·eV^-1) were used as top gate TFTs channel layer, leading to a high mobility (55 cm²/V·s). We suggest that TFTs of high mobility to meet the need of display industries can be benefited by the formation of thin film with high crystalline volume fraction as well as low defect density as a channel layer.

• Proceedings of the Korean Institute of Surface Engineering Conference
• /
• 2018.06a
• /
• pp.102-102
• /
• 2018

Electronic industry had required the finer size and the higher performance of the device. Therefore, 3-D die stacking technology such as TSV (through silicon via) and micro-bump had been used. Moreover, by the development of the 3-D die stacking technology, 3-D structure such as chip to chip (c2c) and chip to wafer (c2w) had become practicable. These technologies led to the appearance of HBM (high bandwidth memory). HBM was type of the memory, which is composed of several stacked layers of the memory chips. Each memory chips were connected by TSV and micro-bump. Thus, HBM had lower RC delay and higher performance of data processing than the conventional memory. Moreover, due to the development of the IT industry such as, AI (artificial intelligence), IOT (internet of things), and VR (virtual reality), the lower pitch size and the higher density were required to micro-electronics. Particularly, to obtain the fine pitch, some of the method such as copper pillar, nickel diffusion barrier, and tin-silver or tin-silver-copper based bump had been utillized. TCB (thermal compression bonding) and reflow process (thermal aging) were conventional method to bond between tin-silver or tin-silver-copper caps in the temperature range of 200 to 300 degrees. However, because of tin overflow which caused by higher operating temperature than melting point of Tin ($232^{\circ}C$), there would be the danger of bump bridge failure in fine-pitch bonding. Furthermore, regulating the phase of IMC (intermetallic compound) which was located between nickel diffusion barrier and bump, had a lot of problems. For example, an excess of kirkendall void which provides site of brittle fracture occurs at IMC layer after reflow process. The essential solution to reduce the difficulty of bump bonding process is copper to copper direct bonding below $300^{\circ}C$. In this study, in order to improve the problem of bump bonding process, copper to copper direct bonding was performed below $300^{\circ}C$. The driving force of bonding was the self-annealing properties of electrodeposited Cu with high defect density. The self-annealing property originated in high defect density and non-equilibrium grain boundaries at the triple junction. The electrodeposited Cu at high current density and low bath temperature was fabricated by electroplating on copper deposited silicon wafer. The copper-copper bonding experiments was conducted using thermal pressing machine. The condition of investigation such as thermal parameter and pressure parameter were varied to acquire proper bonded specimens. The bonded interface was characterized by SEM (scanning electron microscope) and OM (optical microscope). The density of grain boundary and defects were examined by TEM (transmission electron microscopy).

• Laser Solutions
• /
• v.14 no.4
• /
• pp.14-20
• /
• 2011

The advantage of using lasers for through silicon via (TSV) drilling is that they allow higher flexibility during manufacturing because vacuums, lithography, and masks are not required; furthermore, the lasers can be applied to metal and dielectric layers other than silicon. However, conventional nanosecond lasers have disadvantages including that they can cause heat affection around the target area. In contrast, the use of a picosecond laser enables the precise generation of TSVs with a smaller heat affected zone. In this study, a comparison of the thermal and crystallographic defect around laser-drilled holes when using a picosecond laser beam with varing a fluence and repetition rate was conducted. Notably, the higher fluence and repetition rate picosecond laser process increased the experimentally recast layer, surface debris, and dislocation around the hole better than the high fluence and repetition rate. These findings suggest that even the picosecond laser has a heat accumulation effect under high fluence and short pulse interval conditions. To eliminate these defects under the high speed process, the CDE (chemical downstream etching) process was employed and it can prove the possibility to applicate to the TSV industry.

• Proceedings of the Korean Institute of Surface Engineering Conference
• /
• 2016.11a
• /
• pp.181-181
• /
• 2016

Hydrogenated microcrystalline silicon (${\mu}c-Si:H$) films have attracted much attention as materials of the bottom-cells in Si thin film tandem photovoltaics due to their low bandgap and excellent stability against light soaking. However, in PECVD, the source gas $SiH_4$ must be highly diluted by $H_2$, which eventually results in low deposition rate. Moreover, it is known that high-rate ${\mu}c-Si:H$ growth is usually accompanied by a large number of dangling-bond (DB) defects in the resulting films, which act as recombination centers for photoexcited carriers, leading to a deterioration in the device performance. During film deposition, Si nanoparticles generated in $SiH_4$ discharges can be incorporated into films, and such incorporation may have effects on film properties depending on the size, structure, and volume fraction of nanoparticles incorporated into films. Here we report experimental results on the effects of nonoparticles incorporation at the different substrate temperature studied using a multi-hollow discharge plasma CVD method in which such incorporation can be significantly suppressed in upstream region by setting the gas flow velocity high enough to drive nanoparticles toward the downstream region. All experiments were performed with the multi-hollow discharge plasma CVD reactor at RT, 100, and $250^{\circ}C$, respectively. The gas flow rate ratio of $SiH_4$ to $H_2$ was 0.997. The total gas pressure P was kept at 2 Torr. The discharge frequency and power were 60 MHz, 180 W, respectively. Crystallinity Xc of resulting films was evaluated using Raman spectra. The defect densities of the films were measured with electron spin resonance (ESR). The defect density of fims deposited in the downstream region (with nonoparticles) is higher defect density than that in the upstream region (without nanoparticles) at low substrate temperature of RT and $100^{\circ}C$. This result indicates that nanoparticle incorporation can change considerably their film properties depending on the substrate temperature.