• Title/Summary/Keyword: hetero-integration

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A Study on a Hetero-Integration of RF MEMS Switch and DC-DC Converter Using Commercial PCB Process (상용 PCB 공정을 이용한 RF MEMS 스위치와 DC-DC 컨버터의 이종 통합에 관한 연구)

  • Jang, Yeonsu;Yang, Woo-Jin;Chun, Kukjin
    • Journal of the Institute of Electronics and Information Engineers
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    • v.54 no.6
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    • pp.25-29
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    • 2017
  • This paper presents a hetero-integration of electrostatically actuated RF MEMS Switch and step up DC-DC converter on a redistribution layer using commercial PCB process. RF characteristics of Duroid with $56{\Omega}$ impedance GCPW transmission line and that of FR4 with $59{\Omega}$ impedance CPW transmission line were analyzed. From DC to 6GHz, RF characteristics of Duroid were better than that of FR4, insertion loss was 2.08dB lower, return loss was 3.91dB higher, and isolation was 3.33dB higher.

III-V/Si Optical Communication Laser Diode Technology (광통신 III-V/Si 레이저 다이오드 기술 동향)

  • Kim, H.S.;Kim, D.J.;Kim, D.C.;Ko, Y.H.;Kim, K.J.;An, S.M.;Han, W.S.
    • Electronics and Telecommunications Trends
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    • v.36 no.3
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    • pp.23-33
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    • 2021
  • Two main technologies of III-V/Si laser diode for optical communication, direct epitaxial growth, and wafer bonding were studied. Until now, the wafer bonding has been vigorously studied and seems promising for the ideal III-V/Si laser. However, the wafer bonding process is still complicated and has a limit of mass production. The development of a concise and innovative integration method for silicon photonics is urgent. In the future, the demand for high-speed data processing and energy saving, as well as ultra-high density integration, will increase. Therefore, the study for the hetero-junction, which is that the III-V compound semiconductor is directly grown on Si semiconductor can overcome the current limitations and may be the goal for the ideal III-V/Si laser diode.

3-D Hetero-Integration Technologies for Multifunctional Convergence Systems

  • Lee, Kang-Wook
    • Journal of the Microelectronics and Packaging Society
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    • v.22 no.2
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    • pp.11-19
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    • 2015
  • Since CMOS device scaling has stalled, three-dimensional (3-D) integration allows extending Moore's law to ever high density, higher functionality, higher performance, and more diversed materials and devices to be integrated with lower cost. 3-D integration has many benefits such as increased multi-functionality, increased performance, increased data bandwidth, reduced power, small form factor, reduced packaging volume, because it vertically stacks multiple materials, technologies, and functional components such as processor, memory, sensors, logic, analog, and power ICs into one stacked chip. Anticipated applications start with memory, handheld devices, and high-performance computers and especially extend to multifunctional convengence systems such as cloud networking for internet of things, exascale computing for big data server, electrical vehicle system for future automotive, radioactivity safety system, energy harvesting system and, wireless implantable medical system by flexible heterogeneous integrations involving CMOS, MEMS, sensors and photonic circuits. However, heterogeneous integration of different functional devices has many technical challenges owing to various types of size, thickness, and substrate of different functional devices, because they were fabricated by different technologies. This paper describes new 3-D heterogeneous integration technologies of chip self-assembling stacking and 3-D heterogeneous opto-electronics integration, backside TSV fabrication developed by Tohoku University for multifunctional convergence systems. The paper introduce a high speed sensing, highly parallel processing image sensor system comprising a 3-D stacked image sensor with extremely fast signal sensing and processing speed and a 3-D stacked microprocessor with a self-test and self-repair function for autonomous driving assist fabricated by 3-D heterogeneous integration technologies.

Suppression of Shrinkage Mismatch in Hetero-Laminates Between Different Functional LTCC Materials

  • Seung Kyu Jeon;Zeehoon Park;Hyo-Soon Shin;Dong-Hun Yeo;Sahn Nahm
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.36 no.2
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    • pp.151-157
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    • 2023
  • Integrating dielectric materials into LTCC is a convenient method to increase the integration density in electronic circuits. To enable co-firing of the high-k and low-k dielectric LTCC materials in a multi-material hetero-laminate, the shrinkage characteristics of both materials should be similar. Moreover, thermal expansion mismatch between materials during co-firing should be minimized. The alternating stacking of an LTCC with silica filler and that with calcium-zirconate filler was observed to examine the use of the same glass in different LTCCs to minimize the difference in shrinkage and thermal expansion coefficient. For the LTCC of silica filler with a low dielectric constant and that of calcium zirconate filler with a high dielectric constant, the amount of shrinkage was examined through a thermomechanical analysis, and the predicted appropriate fraction of each filler was applied to green sheets by tape casting. The green sheets of different fillers were alternatingly laminated to the thickness of 500 ㎛. As a result of examining the junction, it was observed through SEM that a complete bonding was achieved by constrained sintering in the structure of 'calcium zirconate 50 vol%-silica 30 vol%-calcium zirconate 50 vol%'.

An Analysis and Simulation of sRIO for Implementation of Robot's Hetero-Multi Processor (로봇의 이기종 다중 프로세서 구현을 위한 Serial RapidIO(sRIO) 분석 및 시뮬레이션)

  • Moon, Yong-Seomn;Roh, Sang-Hyun;Jo, Kwang-Hun;Park, Jong-Kyu;Bae, Young-Chul
    • Journal of Advanced Navigation Technology
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    • v.14 no.1
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    • pp.57-65
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    • 2010
  • In this paper, we propose the structure of heterogeneous multiprocessor's concept, which is the structure of the new type of the robot controller, and we introduce an integrating structure method, which is distributed multiprocessor within controller using sRIO. We also perform the computer simulation with using the sRIO IP core which was designed within FPGA as the method for implementation of integrated heterogeneous multiprocessor by sRIO communication. Thus, we verify the result.