• Journal of Power Electronics
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• 제18권5호
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• pp.1523-1535
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• 2018

High-performance Phase-Locked Loops (PLLs) are critical for grid synchronization in grid-tied power electronic applications. In this paper, a new single-phase All Digital Phase-Locked Loop (ADPLL) is proposed. It features fast transient response and good robustness under distorted grid conditions. It is designed for Field Programmable Gate Array (FPGA) implementation. As a result, a high sampling frequency of 1MHz can be obtained. In addition, a new OSG is adopted to track the power frequency, improve the harmonic rejection and remove the dc offset. Unlike previous methods, it avoids extra feedback loop, which results in an enlarged system bandwidth, enhanced stability and improved dynamic performance. In this case, a new parameter optimization method with consideration of loop delay is employed to achieve a fast dynamic response and guarantee accuracy. The Phase Detector (PD) and Voltage Controlled Oscillator (VCO) are realized by a Coordinate Rotation Digital Computer (CORDIC) algorithm and a Direct Digital Synthesis (DDS) block, respectively. The whole PLL system is finally produced on a FPGA. A theoretical analysis and experiments under various distorted grid conditions, including voltage sag, phase jump, frequency step, harmonics distortion, dc offset and combined disturbances, are also presented to verify the fast dynamic response and good robustness of the ADPLL.

• International Journal of Control, Automation, and Systems
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• 제5권1호
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• pp.24-34
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• 2007

Closed-loop active twist control of integral helicopter rotor blades is investigated in this paper for reducing hub vibration induced in forward flight. A four-bladed fully articulated integral twist-actuated rotor system has been designed and tested successfully in wind tunnel in open-loop actuation. The integral twist deformation of the blades is generated using active fiber composite actuators embedded in the composite blade construction. An analytical framework is developed to examine integrally twisted helicopter blades and their aeroelastic behavior during different flight conditions. This aeroelastic model stems from a three-dimensional electroelastic beam formulation with geometrical-exactness, and is coupled with finite-state dynamic inflow aerodynamics. A system identification methodology that assumes a linear periodic system is adopted to estimate the harmonic transfer function of the rotor system. A vibration minimizing controller is designed based on this result, which implements a classical disturbance rejection algorithm with some modifications. Using the established analytical framework, the closed-loop controller is numerically simulated and the hub vibratory load reduction capability is demonstrated.

• 한국전자파학회논문지
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• 제19권2호
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• pp.95-101
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• 2008

본 논문은, '불균형 조건의 메타 재질 구조'를 이용하여 GSM 대역에서 불요파 억제와 효과적인 소형화를 얻는 새로운 대역 통과 여파기 설계 기법을 제시한다. 기존의 반파장 및 025배 파장 공진기 기반의 여파기들과 비교하여, 본 CRLH 여파기는 처음으로 제안되는 유도성 결합 inverter에 의해 0차 공진기들이 결합되고, 이것을 사용함으로써 40$\sim$50 dB 하모닉 억제 효과와 80 %율의 소형화 얻는데 위한 우수한 성능을 보여준다. 이 기법의 타당성이 등가 회로와 분산도의 도출과 함께 성능 예측과 실험을 통해 검증된다.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2000년도 추계학술대회 논문집
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• pp.997-1001
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• 2000

In this paper, the case studies of reducing rotational errors is theoretically done for a grinding spindle with an active magnetic bearing system. The rotational errors acting on the magnetic bearing spindle are due to mass unbalance of rotor, runout, grinding excitation and unmodeled nonlinear dynamics of electromagnets. For the most case, the electrical runout of sensor target is big even in well finished surface, this runout can cause a rotation error amplified by feedback control system. The adaptiveed forward method based on LMS algorithm is discussed to compensate this kind of runout effects, and investigated its effectiveness by numerical simulation and experimental analysis. The electrical runout form the rear sensor target of grind spindle is about 70$\mu\textrm{m}$ with harmonic frequencies. The rotor orbit size in rear bearing is reduced about to 5$\mu\textrm{m}$ due to 1X and 2X rejection by feedforward control.

• 한국초전도학회:학술대회논문집
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• 한국초전도학회 2000년도 High Temperature Superconductivity Vol.X
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• pp.193-196
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• 2000

A new type low-pass filter design method based on a coupled line and transmission line theory is proposed to suppress harmonics by attenuation poles in the stop band. The design formula are derived using the equivalent circuit of a coupled transmission line. The new low-pass filter structure is shown to have attractive properties such as compact size, wide stop band range and low insertion loss. The seventh-order low-pass filter designed by present method has a cutoff frequency of 0.9 CHz with a 0.01 dB ripple level. The coupled line type low-pass filter with strip line configuration was fabricated by using a high-temperature superconducting (HTS : YBa$_2$Cu$_3$O$_{7-{\delta}}$ thin film on MgO(100) substrate. Since the HTS coupled tine type low-pass filter was proposed with five attenuation poles in stop band such as 1.8, 2.5, 4, 5.5, 6.2 GHz. The fabricated low-pass filter has improved the attenuation characteristics up to seven times of the cutoff frequency.

• Journal of Power Electronics
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• 제13권3호
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• pp.447-457
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• 2013

For grid-connected LCL-filtered inverters, resonance yields instability and low bandwidth. As a result, careful designs are required. This paper presents a systematic current control structure, where pole assignment consisting of one or more feedbacks is the inner loop, and the outer loop is the direct grid current control. Several other issues are discussed, such as the inner-loop feedback choices, pole-assignment algorithms, robustness and harmonic rejection. Generally, this kind of strategy has three different types according to the inner-loop feedback choices. Among them, a novel pole-assignment algorithm has been proposed, where the inner control maintains four freely-assigned poles which are just two pairs of conjugated poles located at the fundamental and resonance frequencies separately. It has been found that with the different types, the steady-state and dynamic performances are quite different. Finally, simulations and experiments have been provided to verify the control and design of the proposed methods.

• Journal of Electrical Engineering and Technology
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• 제9권2호
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• pp.569-575
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• 2014

A highly efficient class E power amplifier is demonstrated for application to wireless power transfer system. The amplifier is designed with an L-type matching at the output for harmonic rejection and output matching. The power loss and the effect of each component in the amplifier with the matching circuit are analyzed with the current ratio transmitted to the output load. Inductors with a quality factor of more than 120 are used in a dc feed and the matching circuit to improve transmission efficiency. The single-ended amplifier with 20 V supply voltage shows 7.7 W output power and 90.8% power added efficiency at 6.78 MHz. The wireless power transfer (WPT) system with the amplifier shows 5.4 W transmitted power and 82.3% overall efficiency. The analysis and measurements show that high-Q inductors are required for the amplifier design to realize highly efficient WPT system.

• 센서학회지
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• 제28권4호
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• pp.240-245
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• 2019

Phase interpolation is widely adopted in frequency synthesizers and clock-and-data recovery systems to produce an intermediate phase from two existing phases. The intermediate phase is typically generated by combining two input phases with different weights. Unfortunately, this results in non-uniform phase steps. Alternatively, the intermediate phase can be generated by successive approximation, where the interpolated phase at each approximation stage is obtained using the same weight for the two intermediate phases. As a proof of concept, this study presents a 2-GHz 8-bit successive approximation digital-to-phase converter that is designed using 65-nm CMOS technology. The converter receives an 8-phase clock signal as input, and the most significant bit (MSB) section selects four phases to create two sinusoidal waveforms using a harmonic rejection filter. The remaining least significant bit (LSB) section applies the successive approximation to generate the required intermediate phase. Monte-Carlo simulations show that the proposed converter exhibits 0.46-LSB integral nonlinearity and 0.31-LSB differential nonlinearity with a power consumption of 3.12 mW from a 1.2-V supply voltage.

• 한국전자파학회논문지
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• 제13권8호
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• pp.754-763
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• 2002

본 논문은 결함 접지 구조(defected ground structure, DGS)를 삽입하여 소형화한 증폭기의 개선된 전력 성능을 언급하고 있다. DGS에 의한 부가적인 등가성분에 의하여 전파 지연 특성과 전기적 길이 증가 현상이 나타나는데, 이 성질을 이용하면 DGS를 포함한 전송 선로의 전기적 길이를 원래와 같게 유지하기 위하여 물리적 길이를 줄일 수 있다. 물리적 길이를 줄이더라도 전기적 길이는 같으므로 표준 증폭기(original amplifier)의 정합과 성능이 그대로 유지된다. DGS를 삽입하여 길이를 줄인 전송 선로는 증폭기의 원하는 동작주파수에서는 손실이 거의 없지만 하모닉 주파수에서는 일정량의 손실이 있으므로, 소형화된 증폭기(size-reduced amplifier)가 표준 증폭기보다 근 우수한 하모닉 차단 특성을 근본적으로 내재하고 있다. 따라서 출력측에서 검출되는 하모닉 성분의 크기가 표준 증폭기보다는 더 작을 것으로 예측할 수 있다. 이를 확인하기 위하여 표준 증폭기와 DGS로 소형화한 증폭기의 전력 성능을 측정한 결과, 소형화한 증폭기의 2차 하모닉, IMD3 성분, ACPR이 각각 5 dB, 2-6 dB, 1-4 dB가 개선되었다.

• 한국전자파학회논문지
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• 제16권10호
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• pp.1050-1058
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• 2005

본 논문에서는 40 GHz 대역에서 동작하는 IEEE 802.16 고정 무선 통신 액세스를 위한 소형 저가격 및 광대역의 수신 모듈을 설계하고 구현하는 방법을 제안한다. 제안된 수신 모듈은 우수한 성능을 달성하기 위하여 캐비티 공정을 가지는 다층 LTCC 기술을 사용한다. 수신기는 저잡음 증폭기, 서브-하모닉 믹서, 내장된 이미지 제거필터와 IF 증폭기로 구성된다. 전송 손실과 모듈의 크기를 줄이기 위하여, 각 소자를 연결하기 위한 CB-CPW, 스트립 선로, 본드 와이어 및 천이(transition)들이 사용된다. LTCC는 유전율 7.1인 Dupont사의 DP-943을 사용하고 층수는 6층이며, 각 층의 높이가 100 um이다. 구현된 모듈의 크기는 $20{\times}7.5{\times}1.5\;mm^3$이며, 전체 잡음 지수는 4.8 dB 이하, 하향 변환 이득이 19.83 dB, 입력 P1 dB가 -22.8 dBm이고 이미지 제거값이 36.6 dBc 이상이다. 그리고 $560\~590\;MHz$ 대역의 디지털 TV 신호를 40 GHz 대역으로 상향 변환하여 전송시킨 후, 수신 모듈을 이용하여 시연하였다.