Journal of Sensor Science and Technology (센서학회지)

The Korean Sensors Society (한국센서학회)
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A 2-GHz 8-bit Successive Approximation Digital-to-Phase Converter

2 GHz 8 비트 축차 비교 디지털-위상 변환기

  • Shim, Jae Hoon (School of Electronics Engineering, Kyungpook National Unversity)
  • Received : 2019.06.21
  • Accepted : 2019.07.03
  • Published : 2019.07.31
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Abstract

Phase interpolation is widely adopted in frequency synthesizers and clock-and-data recovery systems to produce an intermediate phase from two existing phases. The intermediate phase is typically generated by combining two input phases with different weights. Unfortunately, this results in non-uniform phase steps. Alternatively, the intermediate phase can be generated by successive approximation, where the interpolated phase at each approximation stage is obtained using the same weight for the two intermediate phases. As a proof of concept, this study presents a 2-GHz 8-bit successive approximation digital-to-phase converter that is designed using 65-nm CMOS technology. The converter receives an 8-phase clock signal as input, and the most significant bit (MSB) section selects four phases to create two sinusoidal waveforms using a harmonic rejection filter. The remaining least significant bit (LSB) section applies the successive approximation to generate the required intermediate phase. Monte-Carlo simulations show that the proposed converter exhibits 0.46-LSB integral nonlinearity and 0.31-LSB differential nonlinearity with a power consumption of 3.12 mW from a 1.2-V supply voltage.

Keywords

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Fig. 1. Concept of phase interpolation

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Fig. 2. Nonlinearity of phase interpolation

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Fig. 3. Tournament-style phase interpolation.

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Fig. 4. Successive approximation phase interpolation.

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Fig. 5. Overall structure of the digital-phase converter

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Fig. 6. Phase selection octant.

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Fig. 7. Principle of harmonic rejection.

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Fig. 8. Analog MUX and harmonic rejection filter.

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Fig. 9. The phase interpolator consisting of analog MUX and inverter-based summing amplifiers.

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Fig. 10. Simulated INL/DNL.

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Fig. 11. Distribution of DNL over process variations.

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Fig. 12. Settling behavior of the output phase.

Table 1. Performance summary

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