• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.281-284
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• 2001

This paper describes an analog multi-phase delay-locked loop (DLL) to solve the harmonic lock problem using current-starved inverter and shunt-capacitor delay cell. The DLL can be used not only as an internal clock buffer of microprocessors and memory It's but also as a multi-phase clock generator for gigabit serial interfaces. The proposed circuit was simulated in a 0.25${\mu}{\textrm}{m}$ CMOS technology to solve harmonic lock problem and to realize fast lock-on time and low-jitter we verified time interval less than 40 ps as the simulation results.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.10a
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• pp.259-262
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• 2012

This paper describes a delay-locked loop (DLL) that generates a 64-phase clock with the operating frequency of 125MHz. The proposed DLL use a $4{\times}8$ matrix-based delay line to improve the linearity of a delay line. The output clock with 64-phase is generated by using a CMOS multiplex and a inverted-based interpolator from 32-phase clock which is the output clock of the $4{\times}8$ matrix-based delay line. The circuit for an initial phase lock, which is independent on the duty cycle ratio of the input clock, is used to prevent from the harmonic lock of a DLL. The proposed DLL is designed using a $0.18-{\mu}m$ CMOS process with a 1.8 V supply. The simulated operating frequency range is 40 MHz to 200 MHz. At the operating frequency of a 125 MHz, the worst phase error and jitter of a 64-phase clock are +11/-12 ps and 6.58 ps, respectively.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.14 no.7
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• pp.2891-2903
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• 2020

Phase-generated carrier (PGC) demodulation algorithm is the main demodulation methods in Fiber-optic interferometric sensors (FOISs). The conventional PGC demodulation algorithms are influenced by the carrier phase delay between the interference signal and the carrier signal. In this paper, an automatic carrier phase delay synchronization (CPDS) algorithm based on orthogonal phase-locked technique is proposed. The proposed algorithm can calculate the carrier phase delay value. Then the carrier phase delay can be compensated by adjusting the initial phase of the fundamental carrier and the second-harmonic carrier. The simulation results demonstrate the influence of the carrier phase delay on the demodulation performance. PGC-Arctan demodulation system based on CPDS algorithm is implemented on SoC. The experimental results show that the proposed algorithm is able to obtain and eliminate the carrier phase delay. In comparison to the conventional demodulation algorithm, the signal-to-noise and distortion ratio (SINAD) of the proposed algorithm increases 55.99dB.

• Journal of Power Electronics
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• v.12 no.4
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• pp.654-663
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• 2012

In this paper, a digital control strategy based on equivalent fundamental and odd harmonic resonators is proposed for single-phase DVRs. By using a delay block, which can be equivalent to a bank of resonators, it rejects the fundamental and odd harmonic disturbances effectively. The structure of the single closed-loop control system consists of a delay block, a proportional gain and a set of zero phase notch filters. The principle of the controller design is discussed in detail to ensure the stability of the system. Both the supply voltage and the load current feedforwards are used to improve the response speed and the ability to eliminate disturbances. The proposed controller is simple in terms of its structure and implementation. It has good performances in harmonic compensation and dynamic response. Experimental results from a 2kW DVR prototype confirm the validity of the design procedure and the effectiveness of the control strategy.

• Journal of IKEEE
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• v.21 no.4
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• pp.416-419
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• 2017

In this paper, we propose a new digital delay-locked loop (DLL) for high-speed DDR3/DDR4 SDRAMs. The proposed digital DLL adopts a fine delay line using phase interpolation to eliminate the jitter increase problem due to the boundary switching problem. In addition, the proposed digital DLL utilizes a new gradual search algorithm to eliminate the harmonic lock problem. The proposed digital DLL is designed with a 1.1 V, 38-nm CMOS DRAM process and has a frequency operating range of 0.25-2.0 GHz. It has a peak-to-peak jitter of 1.1 ps at 2.0 GHz and has a power consumption of about 13 mW.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.54 no.8
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• pp.377-386
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• 2005

This paper presents the control algorithm of single-phase hybrid active power filter for the compensation of harmonic current components in nonlinear R-L load with passive active Power filters. To construct two phase system, an imaginary second phase was made. In this proposed method, the new signal which is the delayed through the filtering by the phase-delay property of low-pass filter is used as the secondary phase. Because two-phases have the different phase, the instantaneous calculation of harmonic current is possible. In this paper, a reference voltage is created by multiplying the coefficient k by the compensation current using the rotating reference frame synchronized with the source-frequency, not applying to instantaneous reactive power theory which has been used with the existing fixed reference frames In order to verify the validities of the proposed control methods, experiments are carried out with the prototypes of single-phase hybrid active power filter.

• Journal of Power Electronics
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• v.9 no.5
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• pp.718-725
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• 2009

To get instantaneous reference data in a single power system with vector space phasors, the instantaneous load current is adopted as a phase and another new signal, which is delayed through filtering by the phase-delay property of a low-pass filter, is used as the secondary phase. Because the two-phases have a different phase, the instantaneous value of the harmonic current can be obtained without a time-delay in calculation. The reference voltage is created by multiplying the coefficient k by the compensation current using the rotating reference frame synchronized with the source-frequency. To verify the validity of the proposed control method, experiments are carried out on a prototype of the single-phase hybrid active power filter system.

• Proceedings of the KIEE Conference
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• 2005.04a
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• pp.149-151
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• 2005

This paper deals with the novel control algorithm of single-phase hybrid active power filter for the compensation of harmonic current components in nonlinear R-L load with passive active power filters. To construct two-axes coordinate, an imaginary second phase was made by giving time delay to line current. In this proposed method, the new signal, which was the delayed through the filtering by the phase-delay property of low-pass filter, is used as the secondary phase. Because two phases have different phase, instantaneous calculation of harmonic current is possible. In this paper, a reference voltage is created by multiplying gain of filter by compensation current using the rotating reference frames that synchronizes with source-frequency, not applying to instantaneous reactive power theory which has been used with the existing fixed reference frames. This paper shows the experimental results, which provide a high accuracy and extremely fast response of single-phase hybrid active Bower filter under the operation with the proposed control method.

• Journal of Power Electronics
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• v.10 no.4
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• pp.412-418
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• 2010

This paper proposes a new algorithm to generate a reference signal for an active power filter using a sliding-window FFT operation to improve the steady-state performance of the active power filter. In the proposed algorithm the sliding-window FFT operation is applied to the load current to generate the reference value for the compensating current. The magnitude and phase-angle for each order of harmonics are respectively averaged for 14 periods. Furthermore, the phase-angle delay for each order of harmonics passing through the controller is corrected in advance to improve the compensation performance. The steady-state and transient performance of the proposed algorithm was verified through computer simulations and experimental work with a hardware prototype. A single-phase active power filter with the proposed algorithm can offer a reduction in THD from 75% to 4% when it is applied to a non-linear load composed of a diode bridge and a RC circuit. The active power filter with the proposed reference generation method shows accurate harmonic compensation performance compared with previously developed methods, in which the THD of source current is higher than 5%.

• The Transactions of the Korean Institute of Power Electronics
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• v.24 no.3
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• pp.215-227
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• 2019

Grid-connected inverters should satisfy a certain level of total harmonic distortion (THD) to meet harmonics standards, such as IEEE 519 and P1547. The output quality of an inverter is typically degraded due to grid voltage harmonics, dead time effects, and the device's turn-on/turn-off delay, which all contribute to increasing the THD value of the output. The use of a harmonic controller is essential to meet the required THD value for inverter output under a distorted grid condition. In this study, an improved feedforward harmonic compensation method is proposed to effectively eliminate low-order harmonics in the inverter current to the grid. In the proposed method, harmonic components are directly compensated through feedforward terms generated by the proportional resonant controller with the grid current in a stationary frame. The proposed method is simple to implement but powerful in eliminating harmonics from the output. The effectiveness of the proposed method is verified through simulation using PSIM software and experiments with a 5 kW single-phase grid-connected inverter.