• Title/Summary/Keyword: hardware cost

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Compensation of Resistance Variation due to Temperature in Voltage Measurement System (온도에 따른 저항 변화를 보상한 전압 측정 방법)

  • Min, Sang-Jun;Kim, Jin-Sung
    • Journal of the Korean Society for Precision Engineering
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    • v.29 no.11
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    • pp.1174-1177
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    • 2012
  • In voltage measurement by using voltage divider with series resistors, error is generated caused by the variation of resistance. In order to reduce these errors, the hardware cost tends to increase in the previous works. In the proposed method, three resistors are used for the voltage divider of which the organization is adjusted by using switches. Three voltages are measured and the ratio of resistance is calculated based on the measured voltages. Since the resistance ratio is calculated by measuring voltages and additional hardware cost is minimal, the voltage can be measured with high accuracy and low cost. Experimental results show that the mean absolute error is 12.1 mV when the input voltage ranges from 5 V to 50 V.

Comparison of Paper-Pencil and Hardware Tests for Investigating Stereotypes for Controls of Passenger Cars (승용 자동차 조종장치 스테레오타입 조사를 위한 설문조사와 실물 시뮬레이션 방법 비교)

  • Kee, Dohyung
    • Journal of the Korea Safety Management & Science
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    • v.15 no.2
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    • pp.63-69
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    • 2013
  • The purposes of this study are to survey stereotypes of control-display relationships for seven principal controls in passenger cars using the paper-pencil and hardware tests, and to examine stereotype strength of the paper-pencil test through comparing the stereotypes for the controls derived by the two methods. Ninety two and 60 college-aged students participated in the paper-pencil test and the real car simulation of the hardware test, respectively. There are dominant motion-directions for all controls in the paper-pencil test, while in the hardware test, there are dominant motion-directions for six controls including head light, high beam, door window, ignition key, door key and door lock controls. The stereotypes of motion-directions for six controls obtained by the paper-pencil test were the same as or similar to those by the hardware test. It was inferred from this that the congruence of the stereotypes by the two methods might be attributed to two simple motion-direction principles of 'clockwise for increase' and 'upward for increase.' Although it is known that the hardware test would be best for obtaining accurate stereotypes between controls and displays, this study implies that if the paper-pencil test is well designed, the paper-pencil test can produce the same results as the hardware test at low cost and without consuming time.

The Design of Hardware MPI Units for MPSoC (MPSoC를 위한 저비용 하드웨어 MPI 유닛 설계)

  • Jeong, Ha-Young;Chung, Won-Young;Lee, Yong-Surk
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.36 no.1B
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    • pp.86-92
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    • 2011
  • In this paper, we propose a novel hardware MPI(Message Passing Interface) unit which supports message passing in multiprocessor system which use distributed memory architecture. MPI Hardware unit processes data synchronization, transmission and completion, and it supports processor non-blocking operation so it reduces overhead according to synchronization. Additionally, MPI hardware unit combines ready entry, request entry, reserve entry which save and manage the synchronized messages and performs the multiple outstanding issue and out of order completion. According to BFM(Bus Functional Model) simulation result, the performance is increased by 25% on many to many communication. After we designed MPI unit using HDL, with synopsys design compiler we synthesized, and for synthesis library we used MagnaChip $0.18{\mu}m$. And then we making prototype chip. The proposed message transmission interface hardware shows high performance for its increase in size. Thus, as we consider low-cost design and scalability, MPI hardware unit is useful in increasing overall performance of embedded MPSoC(Multi-Processor System-on-Chip).

A Study on the Design Plan of Naval Combat System Software to Reduce Cost of Hardware Discontinuation Replacement

  • Jeong-Woo, Son
    • Journal of the Korea Society of Computer and Information
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    • v.28 no.1
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    • pp.71-78
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    • 2023
  • In this paper, we analyze the structure of TV video software, one of the warship combat management system software, and propose a standard architecture that minimizes software modification due to the discontinuation replacement of warship hardware. The class structure was newly designed to minimize the class modified when replacing the warship hardware by separating the variable elements and common elements of TV video software through FORM(Feature-Oriented Reuse Method), the common part that communicates with the warship combat management system and displays the TV screen and the variable part that communicates between the operator and the TV camera. In addition, the Strategy design pattern is applied to efficiently add and modify classes that directly use hardware-dependent APIs when replacing hardware discontinuation, and to make both discontinued and replacements available software. Finally, the reliability testing time and functional testing time of the existing TV video software and the proposed software were measured and compared, and finally, it was confirmed that the hardware discontinuation replacement cost was reduced.

Design of Cryptographic Hardware Architecture for Mobile Computing

  • Kim, Moo-Seop;Kim, Young-Sae;Cho, Hyun-Sook
    • Journal of Information Processing Systems
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    • v.5 no.4
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    • pp.187-196
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    • 2009
  • This paper presents compact cryptographic hardware architecture suitable for the Mobile Trusted Module (MTM) that requires low-area and low-power characteristics. The built-in cryptographic engine in the MTM is one of the most important circuit blocks and contributes to the performance of the whole platform because it is used as the key primitive supporting digital signature, platform integrity and command authentication. Unlike personal computers, mobile platforms have very stringent limitations with respect to available power, physical circuit area, and cost. Therefore special architecture and design methods for a compact cryptographic hardware module are required. The proposed cryptographic hardware has a chip area of 38K gates for RSA and 12.4K gates for unified SHA-1 and SHA-256 respectively on a 0.25um CMOS process. The current consumption of the proposed cryptographic hardware consumes at most 3.96mA for RSA and 2.16mA for SHA computations under the 25MHz.

Vehicle dynamic analysis of continuously controlled semi-active suspension using hardware-in-the-loop simulation (Hardware-in-the-loop 시뮬레이션을 이용한 연속 가변식 반능동 현가 시스템의 차량 동역학적 해석)

  • 황성호;허승진;이교일
    • 제어로봇시스템학회:학술대회논문집
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    • 1996.10b
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    • pp.1107-1112
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    • 1996
  • A semi-active suspension system with continuously variable damper is greatly expected to be mainly used in the future as a high-performance suspension system due to its cost-effectiveness, light weight, and low energy consumption. To develop the suitable control logic for the semi-active suspension system, the hardware-in-the-loop simulation is performed with the experimental continuously variable damper combined with a quarter-car model. The hardware-in-the-loop simulation results are compared for passive, on/off controlled, and continuously controlled dampers in the aspects of ride comfort and driving safety, assuming each damper to be installed on a vehicle.

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A Study on an Efficient Solution to the Synonym Problem using Page Alignment (페이지 정렬을 이용한 효과적인 동의어 문제 해결 기법에 관한 연구)

  • 김제성;민상렬;전상훈;안병철;정덕균;김종상
    • Journal of the Korean Institute of Telematics and Electronics B
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    • v.33B no.2
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    • pp.37-46
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    • 1996
  • This paper proposes a cost-effective solution to the synonym problem of virtual caches. In the proposed solution, a minimal hardware addition guarantees the correctness whereas the software counterpart helps improve the performance. The key to this proposed solution is an addition of a small physically-indexed cache called U-cache. The U-cache maintains the reverse translation information of the cache blocks that belong to unaligned virtual pages only, where aligned measns that the lower bits of the virtual page number match those of the corresponding physical page number. The page alignment is a simple software optimization to improve the performance of the U-cche hardware. With the combination of both hardware and software, the proposed solution reduces the hardware costs and minimizes software modification and performance degradation. Performance evaluation base on ATUM traces shows that a U-cache, with only a few entries, performs almost as well as fully-configured hardware-based solution when more than 95% of the pages are aligned.

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Hardware Implementation of Transform and Quantization for H.264/JVT (하드웨어 기반의 H.264/JVT 변환 및 양자화 구현)

  • 임영훈;정용진
    • Proceedings of the IEEK Conference
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    • 2003.11a
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    • pp.83-86
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    • 2003
  • In this paper, we propose a new hardware architecture for integer transform, quantizer operation of a new video coding standard H.264/JVT. We describe the algorithm to derive hardware architecture emphasizing the importance of area for low cost and low power consumption. The proposed architecture has been verified by PCI-interfaced emulation board using APEX-II Altera FPGA and also by ASIC synthesis using Samsung 0.18 ${\mu}{\textrm}{m}$ CMOS cell library. The ASIC synthesis result shows that the proposed hardware can operate at 100 MHz, processing more than 1, 300 QCIF video frames per second. The hardware is going to be used as a core module when implementing a complete H.264 video encoder/decoder ASIC for real-time multimedia application.

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정보시스템 도입 규모추정을 위한 용량산정 방식에 관한 연구

  • Na, Jong-Hoe;Chon, Gwang-Don;Jeong, Hae-Yong
    • Proceedings of the Korea Association of Information Systems Conference
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    • 2005.12a
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    • pp.307-313
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    • 2005
  • According to the Policy for ' e-Korea construction ' of Korean government, investment of information system during the Past decay are dramatically increasing. More than a half of this investment is cost of hardware infrastructure. So, accurate hardware sizing are essential for higher efficiency of investment. Accurate hardware sizing benefits are generally viewed in toms of the avoidance of excess equipment and lost opportunity costs by not being able to support business needs. Unfortunately, however, little research effort to make the hardware sizing methodology are doing. We propose a sizing method for information system in public sector. This method is determinated empirical study that are gathering and analyzing cases, making method and reviewing expert. Finally we are proposed calculating method for hardware components that is CPU, memory, internal and external disk according to the application system type which is OLTP, Web, WAS. Our study certainly will act as a catalyst for higher investment-efficiency of the future information programs in public sector.

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Open-Source Hardware Module Application for Remote Monitoring of Disaster Prevention (재난관리 원격 모니터링용 오픈소스 하드웨어 모듈 응용)

  • Jin, Kyung-Chan;Lee, Eun-Ju;Lee, Sung-Ho
    • Journal of Sensor Science and Technology
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    • v.24 no.5
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    • pp.299-305
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    • 2015
  • Since the natural disasters such as floods, droughts, heat wave and cold wave are increasing, the need for risk management is necessary to minimize the damage with utilizing IT technology. Also, the monitoring services of disaster response type have been developed and applied. Recently, the open source hardware based on the signal of the sensor, or the monitoring studies have been carried. In this paper, by analyzing a low-cost open source hardware platform such as Beagle board, we examine the utilization of the hardware-based module for sensor monitoring.