• IEMEK Journal of Embedded Systems and Applications
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• v.3 no.1
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• pp.19-24
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• 2008

To reduce time-to-market, more and more embedded system developers and system-on-chip designers rely on microprocessor-based design methodology. ARM processor has been a major player in this industry over the last 10 years. However, there are many restrictions on developing embedded software using ARM processor in the early design stage. For those who are not familiar with embedded software development environment or who cannot afford to have an expensive embedded hardware equipment, testing their software on a real ARM hardware platform is a challenging job. To overcome such a problem, we have designed VMA (Virtual ARM Machine), which offers easier testing and debugging environment to ARM based embedded system developers. Major benefits that can be achieved by utilizing a virtual ARM platform are (1) reducing development cost, (2) lowering the entrance barrier for embedded system novices, and (3) making it easier to test and debug embedded software designs. Unlike many other purely software-oriented ARM simulators which are independent of real hardware platforms, VMA is specifically targeted on SYS-Lab 5000 ARM hardware platform, (designed by Libertron, Inc.), which means that VMA imitates behaviors of embedded software as if the software is running on the target embedded hardware as closely as possible. This paper will describe how VMA is designed and how VMA can be used to reduce design time and cost.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.3
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• pp.35-40
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• 2010

In this paper, we propose a hardware resource sharable camera control processor (CCP) for low-cost and low-power camera cell phones. The main idea behind the proposed architecture is that adds direct access paths in the CCP to share its hardware resources so that the baseband processor expands its capabilities and boosts its performance by utilizing CCF's hardware resources. In addition, we applied a module grain dock-gating method to reduce power dissipation. Hence, the CCP can realize low-power and low-cost camera cell phones with greater hardware efficiency. This chip was fabricated in a 0.18um CMOS process with an active area of $3.8mm\;{\times}\;3.8mm$.

• Proceedings of the Korea Multimedia Society Conference
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• 1998.04a
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• pp.366-370
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• 1998

One major limitation of the efficiency of parallel computer designs has been the prohibitively high cost of parallel communication between processors and memories. Linear order concentrators can be used to build theoretically optimal interconnection schemes. Current designs call for building superconcentrators from concentrators, then using these to recursively partition the connection streams O(log2N) times to achieve point-to-point routing. Since the superconcentrators each have O(N) hardware complexity but O(log2N) depth, the resulting networks are optimal in hardware, but they are of O(log2N) depth. This pepth is not better than the O(log2N) depth Bitonic sorting networks, which can be implemented on the O(N) shuffle-exchange network with message passing. This paper introduces a new method of constructing networks using linear order concentrators and expanders, which can be used to build interconnection networks with O(log2N) depth as well as O(Nlog2N) hardware cost. (All logarithms are in base 2 throughout paper)

• IEMEK Journal of Embedded Systems and Applications
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• v.7 no.1
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• pp.17-24
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• 2012

Recently automotive software has been more complex and needs to be reduced its development time. Software testing of its functionalities and performance should be conducted in an early development phase to reduce time to market and the development cost. Software functional testing can be performed through simulating the hardware, but it is not guaranteed that evaluation of real-time performance using simulation has enough accuracy. Real-time performance can be precisely evaluated with hardware-in-the-loop simulation, but it costs time and effort to set up hardware for testing. In this paper, we suggest a testing system that can evaluate functional requirements and real time properties with a general-purpose development board in the early development phase. In addition, we improve reusability of the testing system through modularized and layered architecture. With the proposed testing system we can contribute to building reliable testing system at low cost without difficulty.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.11 no.5
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• pp.475-480
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• 2018

In OFDM-based systems, FFT is a critical component since it occupies large area and consumes more power. In this paper, we present a low hardware-cost and low power 512-point pipelined FFT design method for OFDM applications. To reduce the number of twiddle factors and to choose simple design architecture, the radix-$2^4-2^3$ algorithm are exploited. For twiddle factor multiplication, we propose a new canonical signed digit (CSD) complex multiplier design method to minimize the hardware-cost. In hardware implementation with Intel FPGA, the proposed FFT design achieves more than about 28% reduction in gate count and 18% reduction in power consumption compared to the previous approaches.

• Journal of Information Technology Services
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• v.5 no.1
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• pp.47-59
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• 2006

According to the policy for "e-Korea construction" of Korean government, Investment of information system during the past decade are dramatically increasing. More than a half of this investment is cost of hardware infrastructure. So, accurate hardware sizing are essential for higher efficiency of investment. Accurate hardware sizing benefits are generally viewed in terms of the avoidance of excess equipment and lost opportunity costs by not being able to support business needs. Unfortunately, however, little research effort to make the hardware sizing methodology are doing. We propose a sizing method for information system in public sector. This method is determinate empirical study that are gathering and analyzing cases, making method and reviewing expert. Finally we are proposed calculating method for hardware components that is CPU, memory, internal and external disk according to the application system type which is OLTP, Web, WAS. Our study certainly will act as a catalyst for higher investment-efficiency of the future information programs in public sector.

• 제어로봇시스템학회:학술대회논문집
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• 2000.10a
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• pp.189-189
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• 2000

A controller test on a sounding rocket using a testbed is discussed in the paper. Because of the high cost and the risk for the flight test the hardware simulation on the ground is performed. In this paper the conventional On/Off Controller is applied to the attitude control of a sounding rocket. The hardware simulation results are compared with those of the software simulation.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.6
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• pp.209-221
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• 1994

Timers are commonly used in hardware design for time delays that are to be much longer than the system clock period. In this paper, we present a method by which we can synthesie a hardware containing timers that implement long time delays described in VHDL. Because, in general, timers require high hardware cost, they must be utilized as efficiently as possible. To solve this problem we define a graph model and propose an algorithm that uses the graph model to minimize number of timers. A preliminary experimental result show that the algorithm implements all required time delays using minimum number of timers.

• Transactions of the Korean Society of Automotive Engineers
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• v.15 no.6
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• pp.23-29
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• 2007

In Korea, the number of LPG vehicles is increasing continuously because LPG is cheaper than Gasoline. Also in Europe, the CNG fuel is a good solution to meet $CO_2$ regulation. In order to use LPG/CNG fuel, new EMS ECU must be developed for every type of vehicles and it requires huge development cost. In order to reduce development cost and time, SIEMENS VDO has developed an Interface Box. It supports EMS ECU in the car and manages LPG/CNG fuel injection system. Basically the Interface box can be used with any kind of EMS ECU. The Interface Box controls LPG/CNG injector through the injection command of gasoline EMS ECU. It calculates required amount of based on the fuel temperature and pressure and sends feedback signal to ECU for fuel correction. Also, it controls LPG/CNG specific actuator such a Shut off valves and LPG switch inputs.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.64 no.11
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• pp.1564-1570
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• 2015

This paper intends to suggest a sensing circuit of PWM voltage for a motor emulator operated in the inverter. In the emulation of the motor using a power converter, it is necessary to measure instantaneous voltage at the PWM voltage loaded from the inverter. Using a filter can generate instantaneous voltage, while it is difficult to follow the rapidly changing inverter voltage caused by the propagation delay and signal attenuation. The method of measuring the duty of PWM using FPGA can generate output voltage from the one-cycle delay of PWM, while the cost of hardware is increasing in order to acquire high precision. This paper suggests a PWM voltage sensing circuit using the analogue system that shows high precision, one-cycle delay of PWM and low-cost hardware. The PWM voltage sensing circuit works in the process of integrating input voltage for valid time by comparing levels of three-phase PWM input voltage, and produce the output value integrated at zero vector. As a result of PSIM simulation and the experiment with the produced hardware, it was verified that the suggested circuit in this paper is valid.