Timing Synthesis from VHDL Description

VHDL 표현으로부터의 시간 지연 합성

Timers are commonly used in hardware design for time delays that are to be much longer than the system clock period. In this paper, we present a method by which we can synthesie a hardware containing timers that implement long time delays described in VHDL. Because, in general, timers require high hardware cost, they must be utilized as efficiently as possible. To solve this problem we define a graph model and propose an algorithm that uses the graph model to minimize number of timers. A preliminary experimental result show that the algorithm implements all required time delays using minimum number of timers.