• Journal of Korea Society of Industrial Information Systems
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• v.14 no.2
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• pp.72-80
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• 2009

In this parer, we propose a hardware abstraction architecture(HAA) for low cost flash memories that can be applicable to wireless sensor nodes. The proposed HAA consists of three layers. The three layers are 1) HHL(Hardware Interlace Layer), HAL(Hardware Adaption Layer), and HPL(Hardware Presentation Layer), where HIL provides a platform independent interlace to applications of upper layers, HAL performs hardware resource management, program status control, and generation of logical instructions as main core of the HAA, and HPL initializes hardware and communicates data between MCU and flash memory. We implemented our HAA on AT45DB flash memory, and the HAA used 4,384 bytes program memory and 195 bytes data memory respectively. Since the proposed HAA is composed of well defined three layers and shows a low utilization of memory, it can provides a high efficiency in terms of flexibility, scalability, and re-usability, and thus the HAA is well suited for wireless sensor nodes.

• Journal of the Korea Society of Computer and Information
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• v.22 no.9
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• pp.25-32
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• 2017

In this paper, we propose the softwareization of broadcasting system. Recently, the topic of industry is the fourth industrial revolution. The fourth industrial revolution is evolving from physical to virtualization. The Industrial Revolution is based on IT technology. Artificial Intelligence (AI), Big Data, and the Internet of Things, which are famous for Alpha Go, are based on software. Among IT, software is the main driver of industrial terrain change. The systemization of software on the basis of cloud environment is proceeding rapidly. System development through softwarization can reduce time to market lead time, hardware cost reduction and manual operation compared to existing hardware system. By developing and implementing broadcasting system such as IPTV based on cloud, lead time for opening service compared to existing hardware system can be shortened by more than 90% and investment cost can be saved by about 40%. In addition, the area of the system can be reduced by 50%. In addition, efficiency can be improved between infrastructures, shortening of trouble handling and ease of maintenance. Finally, we can improve customer experience through rapid service opening.

• Journal of IKEEE
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• v.17 no.2
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• pp.202-207
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• 2013

This paper implemented the conventional FAST and BRIEF algorithm as hardware on Zynq-7000 SoC Platform. Previous feature-based hardware accelerator is mostly implemented using the SIFT or SURF algorithm, but it requires excessive internal memory and hardware cost. The proposed FAST & BRIEF accelerator reduces approximately 57% of internal memory usage and 70% of hardware cost compared to the conventional SIFT or SURF accelerator, and it processes 0.17 pixel per Clock.

• Proceedings of the Korean Information Science Society Conference
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• 2005.07a
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• pp.712-714
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• 2005

Real-time 3D visualization of large datasets imposes a distributed architecture of the rendering system and dedicated hardware for image composition. Previous work on this domain has relied on prohibitively expensive cluster systems with hardware composition done by complicated schemes. In this paper we propose a low-cost hardware compositor fur a high performance visualization cluster. We show the system's design and the results obtained using Simulink [1] for our image composition scheme.

• Journal of information and communication convergence engineering
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• v.18 no.1
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• pp.1-7
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• 2020

This paper proposes a fast-processing and low-cost hardware multiple input multiple output (MIMO) channel emulator. The channel emulator is an important component of hardware-based simulation systems. The novelty of this work is the use of sharing and pipelining functions to reduce hardware resource utilization while maintaining a high sample rate. In our proposed emulator, the samples are created sequentially and interpolated to ensure the sample rate is equal to the base band rate. The proposed 4 × 4 MIMO requires low-cost hardware resource so that it can be implemented on a single field-programmable gate array (FPGA) chip. An implementation on Xilinx Virtex-7 VX980T was found to occupy 10.47% of the available configurable slice registers and 12.58% of the FPGA's slice lookup tables. The maximum frequency of the proposed emulator is 758.064 MHz, so up to 560 different paths can be processed simultaneously to generate 560 × 758 million × 2 × 32 bit complex-valued fading samples per second.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.10a
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• pp.112-115
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• 2008

In this paper, we propose H.264 High Profile Encoder Intra Prediction module. This designed module can be operated in 306 cycle for one-macroblock. To verify the Encoder architecture, we developed the reference C from JM 13.2 and verified the our developed hardware using test vector generated by reference C. We adopt plan removal and SAD calculation to reduce the Hardware cost and cycle. The designed circuit can be operated in 133MHz clock system, and has 250K gate counts using TSMC 0.18um process including SRAM memory.

• Journal of Broadcast Engineering
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• v.18 no.5
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• pp.669-679
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• 2013

This paper proposed a new VLSI (Very Large Scale Integrated Circuit) architecture for stereo matching in real time. We minimized the amount of calculation and the number of memory accesses through analyzing calculation of stereo matching. From this, we proposed a new stereo matching calculating cell and a new hardware architecture by expanding it in parallel, which concurrently calculates cost function for all pixels in a search range. After expanding it, we proposed a new hardware architecture to calculate cost function for 2-dimensional region. The implemented hardware can be operated with minimum 250Mhz clock frequence in FPGA (Field Programmable Gate Array) environment, and has the performance of 805fps in case of the search range of 64 pixels and the image size of $640{\times}480$.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.11
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• pp.2045-2049
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• 2008

In this paper, we propose an novel architecture for H.264 High Profile Encoder Intra Prediction module. This designed module can be operated in 306 cycle for one-macroblock. To verify the Encoder architecture, we developed the reference C from JM 13.2 and verified the our developed hardware using test vector generated by reference C. We adopt plan removal and SAD calculation to reduce the Hardware cost and cycle. The designed circuit can be operated in 133MHz clock system, and has 250K gate counts using TSMC 0.18 um process including SRAM memory.

• International Journal of Fuzzy Logic and Intelligent Systems
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• v.13 no.4
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• pp.324-335
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• 2013

This article presents the design, control, and implementation of a small quad-rotor system under the practical limitation of being cost effective for private use, such as in the cases of control education or hobbies involving radio-controlled systems. Several practical problems associated with implementing a small quad-rotor system had to be taken into account to satisfy this cost constraint. First, the size was reduced to attain better maneuverability. Second, the main control hardware was limited to an 8-bit processor such as an AVR to reduce cost. Third, the algorithms related to the control and sensing tasks were optimized to be within the computational capabilities of the available processor within one sampling time. A small quad-rotor system was ultimately implemented after satisfying all of the above practical limitations. Experimental studies were conducted to confirm the control performance and the operational abilities of the system.

• IEMEK Journal of Embedded Systems and Applications
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• v.18 no.5
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• pp.249-257
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• 2023

This paper discusses the increasing need for autonomous delivery robots due to the current growth in the delivery market, rising delivery fees, high costs of hiring delivery personnel, and the need for contactless services. Additionally, the cost of hardware and complex software systems required to build and operate autonomous delivery robots is high. To provide a low-cost alternative to this, this paper proposes a autonomous delivery robot platform using a low-cost sensor combination of 2D LIDAR, depth camera and tracking camera to replace the existing expensive 3D LIDAR. The proposed robot was developed using the RTAB-Map SLAM open source package for 2D mapping and overcomes the limitations of low-cost sensors by using the convex hull algorithm. The paper details the hardware and software configuration of the robot and presents the results of driving experiments. The proposed platform has significant potential for various industries, including the delivery and other industries.